LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult14 is
PORT
( clk :  IN STD_LOGIC;
  Din :  IN SIGNED (8 DOWNTO 0);
 Dout :  OUT SIGNED (11 DOWNTO 0));
END mult14;
ARCHITECTURE a OF mult14 IS
SIGNAL s1 : SIGNED (11 DOWNTO 0);
SIGNAL s2 : SIGNED (10 DOWNTO 0);
SIGNAL s3 : SIGNED (9 DOWNTO 0);
SIGNAL s4 : SIGNED (11 DOWNTO 0);

BEGIN
P1:process(Din)
BEGIN
s1(11 DOWNTO 3)<=Din;
s1( 2 DOWNTO 0)<="000";
s2(10 DOWNTO 2)<=Din;
s2(1  DOWNTO 0)<="00";
s3(9  DOWNTO 1)<=Din;
s3(0)<='0';
if Din(8)='0' then 
s4<=('0'&s1(11 downto 1))+("00"&s2(10 DOWNTO 1))+("000"&s3(9 DOWNTO 1));

else 
s4<=('1'&s1(11 downto 1))+("11"&s2(10 DOWNTO 1))+("111"&s3(9 DOWNTO 1));

end if;
end process;
P2: PROCESS(clk)
BEGIN
if clk'event and clk='1' then
Dout<=s4;
end if;
END PROCESS;
END a;