LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult29 is
PORT
( clk :  IN STD_LOGIC;
  Din :  IN SIGNED (8 DOWNTO 0);
 Dout :  OUT SIGNED (12 DOWNTO 0));
END mult29;
--16+8+4+1
ARCHITECTURE a OF mult29 IS
SIGNAL s1 : SIGNED (12 DOWNTO 0);
SIGNAL s2 : SIGNED (11 DOWNTO 0);
SIGNAL s3 : SIGNED (10 DOWNTO 0);
SIGNAL s4 : SIGNED (12 DOWNTO 0);

BEGIN
P1:process(Din)
BEGIN
s1(12 DOWNTO 4)<=Din;
s1( 3 DOWNTO 0)<="0000";
s2(11 DOWNTO 3)<=Din;
s2(2  DOWNTO 0)<="000";
s3(10 DOWNTO 2)<=Din;
s3(1  DOWNTO 0)<="00";
if Din(8)='0' then 
s4<=('0'&s1(12 downto 1))+("00"&s2(11 DOWNTO 1))+("000"&s3(10 DOWNTO 1))+("00000"&Din(8 DOWNTO 1));

else 
s4<=('1'&s1(12 downto 1))+("11"&s2(11 DOWNTO 1))+("111"&s3(10 DOWNTO 1))+("11111"&Din(8 DOWNTO 1));

end if;
end process;
P2: PROCESS(clk)
BEGIN
if clk'event and clk='1' then
Dout<=s4;
end if;
END PROCESS;
END a;