LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY dff89 IS 
PORT( clk :   IN  STD_LOGIC;
 	  clear : IN  STD_LOGIC;
	  Din :   IN  STD_LOGIC_VECTOR(7 DOWNTO 0); 
	  Dout :  OUT STD_LOGIC_VECTOR(8 DOWNTO 0) ); 
END dff89; 

ARCHITECTURE a OF dff89 IS 
BEGIN 
  PROCESS(clk,clear) 
    BEGIN 
	  IF clear='1' THEN
		 Dout<="000000000";
	  ELSIF clear='0' THEN
	    IF(clk'EVENT AND clk='1') THEN
		 Dout <= (Din(7)&Din);
	    END IF; 
	  END IF; 
  END PROCESS; 
END a;