?? sub141616.vhd
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
ENTITY sub141616 is
PORT(clk : in STD_LOGIC;
Din1 :in signed (13 downto 0);
Din2 :in signed (15 downto 0);
Dout :out signed(15 downto 0));
END sub141616;
ARCHITECTURE a of sub141616 is
SIGNAL s1: signed(15 downto 0);
BEGIN
s1<=(Din1(13)&Din1(13)&Din1);
PROCESS(Din1,Din2,clk)
BEGIN
if clk'event and clk='1' then
Dout<=Din2-s1;
end if;
end process;
end a;
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