LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
ENTITY add121616 is
PORT(clk : in STD_LOGIC;
     Din1 :in signed (11 downto 0);
     Din2 :in signed (15 downto 0);
     Dout:out signed (15 downto 0));
END add121616;
ARCHITECTURE a of add121616 is
SIGNAL s1: signed(15 downto 0);
BEGIN
    s1<=(Din1(11)&Din1(11)&Din1(11)&Din1(11)&Din1);
PROCESS(Din1,Din2,clk)
BEGIN
if clk'event and clk='1' then
Dout<=s1+Din2;
end if;
end process;
end a;