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@Pull Default = PULLUP_UP (2)
@Fast_Bypass Default = None (2)
@ORP_Bypass Default = None
@Input_Registers Default = None (2)
@Register_Powerup Default = None
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Buried Signal Lists.
<A name="Pinout_Listing"></A><FONT COLOR=maroon><U><B><big>Pinout_Listing</big></B></U></FONT>
<BR>
<B> | Pin | Bank |GLB |Assigned| | Signal|
Pin No| Type |Number|Pad |Pin | I/O Type | Type | Signal name
</B>--------------------------------------------------------------------------------------
1 | GND | - | | | | |
2 | TDI | - | | | | |
3 | I_O | 0 |B0 | |LVCMOS18 | Output|<A href=#7>NUMdata_3_</A>
4 | I_O | 0 |B2 | |LVCMOS18 | Output|<A href=#17>NUMlocation_0_</A>
5 | I_O | 0 |B4 | |LVCMOS18 | Output|<A href=#26>VGAr_0_</A>
6 | I_O | 0 |B6 | | | |
7 |GNDIO0 | - | | | | |
8 | I_O | 0 |B8 | | | |
9 | I_O | 0 |B10 | |LVCMOS18 | Output|<A href=#14>UARTtx</A>
10 | I_O | 0 |B12 | |LVCMOS18 | Output|<A href=#25>VGAdena</A>
11 | I_O | 0 |B13 | | | |
12 | IN0 | 0 | | | | |
13 |VCCIO0 | - | | | | |
14 | I_O | 0 |C14 | | | |
15 | I_O | 0 |C12 | |LVCMOS18 | Output|<A href=#18>NUMdata_6_</A>
16 | I_O | 0 |C10 | |LVCMOS18 | Output|<A href=#8>NUMdata_2_</A>
17 | I_O | 0 |C8 | | | |
18 |GNDIO0 | - | | | | |
19 | I_O | 0 |C6 | | | |
20 | I_O | 0 |C5 | | | |
21 | I_O | 0 |C4 | | | |
22 | I_O | 0 |C2 | |LVCMOS18 | Output|<A href=#24>VGAv</A>
23 | IN1 | 0 | | | | |
24 | TCK | - | | | | |
25 | VCC | - | | | | |
26 | GND | - | | | | |
27 | IN2 | 0 | | | | |
28 | I_O | 0 |D13 | | | |
29 | I_O | 0 |D12 | | | |
30 | I_O | 0 |D10 | | | |
31 | I_O | 0 |D8 | | | |
32 |GNDIO0 | - | | | | |
33 |VCCIO0 | - | | | | |
34 | I_O | 0 |D6 | | | |
35 | I_O | 0 |D4 | | | |
36 | I_O | 0 |D2 | | | |
37 | I_O | 0 |D0 | |LVCMOS18 | Output|<A href=#11>NUMlocation_3_</A>
38 |INCLK1 | 0 | | | | |
39 |INCLK2 | 1 | | | | |
40 | VCC | - | | | | |
41 | I_O | 1 |E0 | |LVCMOS18 | Output|<A href=#9>NUMdata_1_</A>
42 | I_O | 1 |E2 | |LVCMOS18 | Output|<A href=#15>NUMlocation_2_</A>
43 | I_O | 1 |E4 | |LVCMOS18 | Output|<A href=#23>VGAh_cs</A>
44 | I_O | 1 |E6 | | | |
45 |VCCIO1 | - | | | | |
46 |GNDIO1 | - | | | | |
47 | I_O | 1 |E8 | | | |
48 | I_O | 1 |E10 | |LVCMOS18 | Output|<A href=#12>NUMdata_7_</A>
49 | I_O | 1 |E12 | |LVCMOS18 | Output|<A href=#16>NUMlocation_1_</A>
50 | I_O | 1 |E14 | | | |
51 | GND | - | | | | |
52 | TMS | - | | | | |
53 | I_O | 1 |F0 | |LVCMOS18 | Output|<A href=#10>NUMdata_0_</A>
54 | I_O | 1 |F2 | | | |
55 | I_O | 1 |F4 | | | |
56 | I_O | 1 |F6 | | | |
57 |GNDIO1 | - | | | | |
58 | I_O | 1 |F8 | | | |
59 | I_O | 1 |F10 | |LVCMOS18 | Output|<A href=#19>NUMdata_5_</A>
60 | I_O | 1 |F12 | | | |
61 | I_O | 1 |F13 | | | |
62 | IN3 | 1 | | | | |
63 |VCCIO1 | - | | | | |
64 | I_O | 1 |G14 | | | |
65 | I_O | 1 |G12 | | | |
66 | I_O | 1 |G10 | |LVCMOS18 | Output|<A href=#28>VGAb_0_</A>
67 | I_O | 1 |G8 | | | |
68 |GNDIO1 | - | | | | |
69 | I_O | 1 |G6 | | | |
70 | I_O | 1 |G5 | | | |
71 | I_O | 1 |G4 | | | |
72 | I_O | 1 |G2 | |LVCMOS18 | Output|<A href=#21>VGAg_1_</A>
73 | IN4 | 1 | | | | |
74 | TDO | - | | | | |
75 | VCC | - | | | | |
76 | GND | - | | | | |
77 | IN5 | 1 | | | | |
78 | I_O | 1 |H13 | | | |
79 | I_O | 1 |H12 | | | |
80 | I_O | 1 |H10 | | | |
81 | I_O | 1 |H8 | | | |
82 |GNDIO1 | - | | | | |
83 |VCCIO1 | - | | | | |
84 | I_O | 1 |H6 | | | |
85 | I_O | 1 |H4 | | | |
86 | I_O | 1 |H2 | |LVCMOS18 | Output|<A href=#22>VGAb_1_</A>
87 | I_O/OE| 1 |H0 | |LVCMOS18 | Output|<A href=#27>VGAg_0_</A>
88 |INCLK3 | 1 | | | | |
89 |INCLK0 | 0 | | |LVCMOS18 | Input |<A href=#13>clk</A>
90 | VCC | - | | | | |
91 | I_O/OE| 0 |A0 | |LVCMOS18 | Output|<A href=#6>NUMdata_4_</A>
92 | I_O | 0 |A2 | |LVCMOS18 | Output|<A href=#20>VGAr_1_</A>
93 | I_O | 0 |A4 | | | |
94 | I_O | 0 |A6 | | | |
95 |VCCIO0 | - | | | | |
96 |GNDIO0 | - | | | | |
97 | I_O | 0 |A8 | | | |
98 | I_O | 0 |A10 | | | |
99 | I_O | 0 |A12 | | | |
100 | I_O | 0 |A14 | | | |
--------------------------------------------------------------------------------------
<Note> GLB Pad : This notation refers to the GLB I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type :
ClkIn : Dedicated input or clock pin
CLK : Dedicated clock pin
I_O : Input/Output pin
INP : Dedicated input pin
JTAG : JTAG Control and test pin
NC : No connected
<A name="Input_Signal_List"></A><FONT COLOR=maroon><U><B><big>Input_Signal_List</big></B></U></FONT>
<BR>
<B> Input
Pin Fanout
Pin GLB Type Pullup Signal
</B>----------------------------------------
89 -- INCLK -------- Up <A name=13>clk</A>
----------------------------------------
<A name="Output_Signal_List"></A><FONT COLOR=maroon><U><B><big>Output_Signal_List</big></B></U></FONT>
<BR>
<B> I C P R P O Output
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
</B>-------------------------------------------------------------------------------
53 F 0 - 0 1 COM -------- Fast Up <A href=#10>NUMdata_0_</A>
41 E 0 - 0 1 COM -------- Fast Up <A href=#9>NUMdata_1_</A>
16 C 0 - 0 1 COM -------- Fast Up <A href=#8>NUMdata_2_</A>
3 B 0 - 0 1 COM -------- Fast Up <A href=#7>NUMdata_3_</A>
91 A 0 - 0 1 COM -------- Fast Up <A href=#6>NUMdata_4_</A>
59 F 0 - 0 1 COM -------- Fast Up <A href=#19>NUMdata_5_</A>
15 C 0 - 0 1 COM -------- Fast Up <A href=#18>NUMdata_6_</A>
48 E 0 - 0 1 COM -------- Fast Up <A href=#12>NUMdata_7_</A>
4 B 0 - 0 1 COM -------- Fast Up <A href=#17>NUMlocation_0_</A>
49 E 0 - 0 1 COM -------- Fast Up <A href=#16>NUMlocation_1_</A>
42 E 0 - 0 1 COM -------- Fast Up <A href=#15>NUMlocation_2_</A>
37 D 0 - 0 1 COM -------- Fast Up <A href=#11>NUMlocation_3_</A>
9 B 0 - 0 1 COM -------- Fast Up <A href=#14>UARTtx</A>
66 G 6 2 4 1 DFF R 1 ------G- Fast Up <A href=#28>VGAb_0_</A>
86 H 5 2 3 1 DFF R 1 -------H Fast Up <A href=#22>VGAb_1_</A>
10 B 17 4 6 2 DFF R 5 AB---FGH Fast Up <A href=#25>VGAdena</A>
87 H 6 2 4 1 DFF R 1 -------H Fast Up <A href=#27>VGAg_0_</A>
72 G 5 3 3 1 DFF R 1 ------G- Fast Up <A href=#21>VGAg_1_</A>
43 E 10 3 8 2 DFF R 2 -B--E--- Fast Up <A href=#23>VGAh_cs</A>
5 B 6 3 4 1 DFF R 1 -B------ Fast Up <A href=#26>VGAr_0_</A>
92 A 7 3 3 2 DFF R 1 A------- Fast Up <A href=#20>VGAr_1_</A>
22 C 19 2 11 3 DFF R 2 -BC----- Fast Up <A href=#24>VGAv</A>
-------------------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
<A name="Bidir_Signal_List"></A><FONT COLOR=maroon><U><B><big>Bidir_Signal_List</big></B></U></FONT>
<BR>
<B> I C P R P O Bidir
N L Mc R E U C O F B Fanout
Pin GLB P LL PTs S Type E S P E E P P Slew Pullup Signal
</B>-----------------------------------------------------------------------
-----------------------------------------------------------------------
<Note> CLS = Number of clusters used
INP = Number of input signals
PTs = Number of product terms
LL = Number of logic levels
PRE = Has preset equation
RES = Has reset equation
PUP = Power-Up initial state: R=Reset, S=Set
CE = Has clock enable equation
OE = Has output enable equation
FP = Fast path used
OBP = ORP bypass used
<A name="Buried_Signal_List"></A><FONT COLOR=maroon><U><B><big>Buried_Signal_List</big></B></U></FONT>
<BR>
<B> I C P R P Node
N L Mc R E U C I F Fanout
Mc GLB P LL PTs S Type E S P E R P Signal
</B>------------------------------------------------------------------------
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