library ieee;
use ieee.std_logic_1164.all;

entity fenpin is
port(clk_in:  in   std_logic;
     clk_out: out  std_logic);
end fenpin;
architecture first of fenpin is
constant fpb: integer:=10;
signal   aqi: integer range 0 to fpb;
begin
process(clk_in)
begin
if rising_edge(clk_in) then
   if aqi<fpb then
      aqi<=aqi+1;
      clk_out<='0';
   else
      aqi<=0;
      clk_out<='1';
   end if;
end if;
end process;
end first;