library ieee;
use ieee.std_logic_1164.all;
entity def1 is
    port( clk : in std_logic;
          d   : in std_logic;
          q   : out std_logic);
end def1;
architecture bhv of def1 is
    signal q1: std_logic;   ---???
begin
    process(clk)
    begin
    if clk'event and clk='1' then q1<=d;
    end if;
    q<=q1;           --     ???
    end process;
end bhv;