LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TLC5510 IS
	PORT(	CLK 	: 	IN	STD_LOGIC;	--采樣控制Cctl_GP_LatchFlag輸入
			D		: 	IN	STD_LOGIC_VECTOR(7 DOWNTO 0);	--8位AD數據
			ADCLK	: 	OUT	STD_LOGIC;	--TLC5510的CLK
			ADOE	: 	OUT STD_LOGIC;	--TLC5510的OE輸出使能低電平有效
			DATA	: 	OUT STD_LOGIC_VECTOR(7 DOWNTO 0));	--8位數據

END ENTITY TLC5510;


ARCHITECTURE behavioural OF TLC5510 IS

	TYPE 	ADS_STATES IS (State0_typ,State1_typ);
	
	SIGNAL	sta_G_CurrentState	:	ADS_STATES;
	SIGNAL  sta_G_NextState 	:	ADS_STATES;
	SIGNAL  ctl_GP_LatchFlag 	:	STD_LOGIC;

BEGIN

COM:	PROCESS(sta_G_CurrentState)	--A/D采樣控制狀態機
		BEGIN
			CASE sta_G_CurrentState IS
				WHEN State0_typ => ADCLK <= '1' ; ctl_GP_LatchFlag <= '1' ; --DCLK <= '0';
					sta_G_NextState <= State1_typ;
				WHEN State1_typ => ADCLK <= '0' ; ctl_GP_LatchFlag <= '0' ; --DCLK <= '1';
					sta_G_NextState <= State0_typ;
				WHEN OTHERS => ADCLK <='0' ; ctl_GP_LatchFlag <= '0' ; --DCLK <= '1';
					sta_G_NextState <= State0_typ;
			END CASE;
		END PROCESS COM;

REG:	PROCESS (CLK)	--狀態機驅動進程
		BEGIN 
			IF(CLK'EVENT AND CLK = '1')THEN
				sta_G_CurrentState <= sta_G_NextState;
			END IF;
		END PROCESS REG;

LATCH:	PROCESS(ctl_GP_LatchFlag)--ctl_GP_LatchFlag上升沿鎖存數據
		BEGIN
			IF ctl_GP_LatchFlag'EVENT AND ctl_GP_LatchFlag = '1'  THEN  DATA <= D;
			END IF;
		END PROCESS LATCH;
		
ADOE <= '0';

END ARCHITECTURE behavioural;