library ieee;
use ieee.std_logic_1164.all;
entity adc_kongzhi is
    port(d:in std_logic_vector(7 downto 0);
         clk,eoc:in std_logic;
         start,ale,oe,lock0:out std_logic;
         q:out std_logic_vector(7 downto 0));
end;
architecture a of adc_kongzhi is
type states is(st0,st1,st2,st3,st4);
signal current_state,next_state:states:=st1;
signal regl:std_logic_vector(7 downto 0);
signal lock:std_logic;
begin
    q<=regl;
    lock0<=lock;
    process(clk)
    begin
      if clk'event and clk='1' then
         case current_state is
              when st0=>start<='0';ale<='0';oe<='0';
                        lock<='0';current_state<=st1;
              when st1=>start<='1';ale<='1';oe<='0';
                        lock<='0';current_state<=st2;
              when st2=>start<='0';ale<='0';oe<='0';
                        lock<='0';
                        if (eoc='1') then
                               current_state<=st3;
                        else   current_state<=st2;
                        end if;
              when st3=>start<='0';ale<='0';oe<='1';
                        lock<='0';current_state<=st4;
              when st4=>start<='0';ale<='0';oe<='1';
                        lock<='1';current_state<=st0;
              when others=>current_state<=st0;
         end case;
         --current_state<=next_state;
      end if;
    end process;
    process(lock)
    begin
      if lock'event and lock='1' then
         regl<=d;
      end if;
    end process;
end;