library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity key_press is
port(clk1:in std_logic;
		row:in std_logic_vector(3 downto 0);
		key_pre:out std_logic);
end key_press;
architecture behav of key_press is
signal sig_1,counter:std_logic_vector(3 downto 0);
signal tmp1,sig_2,sig_3:std_logic;
begin
sig_1<=row;
tmp1<=sig_1(0) and sig_1(1) and sig_1(2) and sig_1(3);
key_pre<=counter(0) and counter(1) and counter(2) and counter(3);

process(clk1)
begin
if(clk1'event and clk1='1')then
   if(sig_3='0')then
    counter<="0000";
    else
   counter<=counter+'1';
end if;
end if;
end process;

process(clk1)
begin
if(clk1'event and clk1='1')then
    if(tmp1='0')then
       if(sig_2='0')then
          sig_2<='1';
        end if;
    elsif(sig_3='0')then
    sig_2<='0';
    end if;
end if;
end process;

process(sig_2,counter)
begin
     if(sig_2='1')then
        if(counter="1111")then
        sig_3<='0';
        else
        sig_3<='1';
     end if;
    end if;
end process;
end behav;