LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY f_adder1 IS
   port(ain,bin,cin: IN STD_LOGIC;
	     cout,sum:out STD_LOGIC);

END ENTITY f_adder1;
ARCHITECTURE fd1 OF f_adder1 IS
COMPONENT h_adder1
   PORT (a,b: IN STD_LOGIC;
          co,so: OUT STD_LOGIC);
      END COMPONENT;
COMPONENT or2a
   PORT (a,b: IN STD_LOGIC;
          c: OUT STD_LOGIC);
      END COMPONENT;
 SIGNAL d,e,f : STD_LOGIC;
    begin
    u1:h_adder1 PORT MAP(a=>ain,b=>bin,
                   co=>d,so=>e);
    u2:h_adder1 PORT MAP(a=>e,b=>cin,
                   co=>f,so=>sum);
    u3:or2a PORT MAP(a=>d,b=>f,
                   c=>cout);
  END ARCHITECTURE fd1;