;     -- arithmetic mode                      ; 30    ;
; Total registers                             ; 41    ;
; I/O pins                                    ; 9     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 41    ;
; Total fan-out                               ; 430   ;
; Average fan-out                             ; 2.81  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                    ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name    ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------+
; |show                      ; 103 (0)           ; 41 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 9    ; 0            ; |show                  ;
;    |receive:inst|          ; 72 (72)           ; 41 (41)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |show|receive:inst     ;
;    |seg_decode:inst6|      ; 31 (31)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |show|seg_decode:inst6 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; receive:inst|b3                                    ; receive:inst|temp   ; yes                    ;
; receive:inst|b8                                    ; receive:inst|temp   ; yes                    ;
; receive:inst|b1                                    ; receive:inst|temp   ; yes                    ;
; receive:inst|b4                                    ; receive:inst|temp   ; yes                    ;
; receive:inst|b5                                    ; receive:inst|temp   ; yes                    ;
; receive:inst|b6                                    ; receive:inst|temp   ; yes                    ;
; receive:inst|b7                                    ; receive:inst|temp   ; yes                    ;
; receive:inst|b2                                    ; receive:inst|temp   ; yes                    ;
; Number of user-specified and inferred latches = 8  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 41    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------+
; Source assignments for receive:inst   ;
+----------------+-------+------+-------+
; Assignment     ; Value ; From ; To    ;
+----------------+-------+------+-------+
; POWER_UP_LEVEL ; Low   ; -    ; i[0]  ;
; POWER_UP_LEVEL ; Low   ; -    ; i[1]  ;
; POWER_UP_LEVEL ; Low   ; -    ; i[2]  ;
; POWER_UP_LEVEL ; Low   ; -    ; i[3]  ;
; POWER_UP_LEVEL ; Low   ; -    ; i[4]  ;
; POWER_UP_LEVEL ; Low   ; -    ; i[5]  ;
; POWER_UP_LEVEL ; Low   ; -    ; i[6]  ;
; POWER_UP_LEVEL ; Low   ; -    ; i[7]  ;
; POWER_UP_LEVEL ; Low   ; -    ; i[8]  ;
; POWER_UP_LEVEL ; Low   ; -    ; i[9]  ;
; POWER_UP_LEVEL ; Low   ; -    ; i[10] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[11] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[12] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[13] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[14] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[15] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[16] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[17] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[18] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[19] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[20] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[21] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[22] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[23] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[24] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[25] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[26] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[27] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[28] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[29] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[30] ;
; POWER_UP_LEVEL ; Low   ; -    ; i[31] ;
; POWER_UP_LEVEL ; Low   ; -    ; temp  ;
+----------------+-------+------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Nov 13 18:35:13 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off show -c show
Info: Found 2 design units, including 1 entities, in source file seg_decode.vhd
    Info: Found design unit 1: seg_decode-seg_decode_arch
    Info: Found entity 1: seg_decode
Info: Found 2 design units, including 1 entities, in source file receive.vhd
    Info: Found design unit 1: receive-receive_arth
    Info: Found entity 1: receive
Warning: Can't analyze file -- file D:/alter/show/show2.vhd is missing
Info: Found 1 design units, including 1 entities, in source file show.bdf
    Info: Found entity 1: show
Info: Elaborating entity "show" for the top level hierarchy
Info: Elaborating entity "seg_decode" for hierarchy "seg_decode:inst6"
Info: Elaborating entity "receive" for hierarchy "receive:inst"
Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable "b1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable "b2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable "b3", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable "b4", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable "b5", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable "b6", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable "b7", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable "b8", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for "b8"
Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for "b7"
Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for "b6"
Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for "b5"
Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for "b4"
Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for "b3"
Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for "b2"
Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for "b1"
Info: Implemented 112 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 7 output pins
    Info: Implemented 103 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Processing ended: Tue Nov 13 18:35:18 2007
    Info: Elapsed time: 00:00:06