?? show.vwf

?? DE2平臺鍵控傳輸
?? VWF
?? 第 1 頁 / 共 2 頁
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上一頁 12
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}

TRANSITION_LIST("a")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2.0;
	}
}

TRANSITION_LIST("b")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2.0;
	}
}

TRANSITION_LIST("c")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2.0;
	}
}

TRANSITION_LIST("d")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2.0;
	}
}

TRANSITION_LIST("e")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2.0;
	}
}

TRANSITION_LIST("f")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2.0;
	}
}

TRANSITION_LIST("g")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 2.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "clk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "dat";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "a";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "b";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "c";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "d";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "e";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "f";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "g";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 0;
}

TIME_BAR
{
	TIME = 1999;
	MASTER = TRUE;
}
;
上一頁 12
?? 文件大小 523 K
?? 上傳用戶 hufei108
?? 所屬分類 VHDL/FPGA/Verilog
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?? show.vwf

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