?? show.tan.qmsg
字號:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register receive:inst\|i\[26\] register receive:inst\|i\[31\] 146.05 MHz 6.847 ns Internal " "Info: Clock \"clk\" has Internal fmax of 146.05 MHz between source register \"receive:inst\|i\[26\]\" and destination register \"receive:inst\|i\[31\]\" (period= 6.847 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.633 ns + Longest register register " "Info: + Longest register to register delay is 6.633 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns receive:inst\|i\[26\] 1 REG LCFF_X50_Y23_N21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X50_Y23_N21; Fanout = 3; REG Node = 'receive:inst\|i\[26\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { receive:inst|i[26] } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.035 ns) + CELL(0.371 ns) 1.406 ns receive:inst\|LessThan0~533 2 COMB LCCOMB_X51_Y24_N28 1 " "Info: 2: + IC(1.035 ns) + CELL(0.371 ns) = 1.406 ns; Loc. = LCCOMB_X51_Y24_N28; Fanout = 1; COMB Node = 'receive:inst\|LessThan0~533'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.406 ns" { receive:inst|i[26] receive:inst|LessThan0~533 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.265 ns) + CELL(0.150 ns) 1.821 ns receive:inst\|LessThan0~534 3 COMB LCCOMB_X51_Y24_N4 1 " "Info: 3: + IC(0.265 ns) + CELL(0.150 ns) = 1.821 ns; Loc. = LCCOMB_X51_Y24_N4; Fanout = 1; COMB Node = 'receive:inst\|LessThan0~534'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.415 ns" { receive:inst|LessThan0~533 receive:inst|LessThan0~534 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.420 ns) 2.498 ns receive:inst\|LessThan0~535 4 COMB LCCOMB_X51_Y24_N30 56 " "Info: 4: + IC(0.257 ns) + CELL(0.420 ns) = 2.498 ns; Loc. = LCCOMB_X51_Y24_N30; Fanout = 56; COMB Node = 'receive:inst\|LessThan0~535'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.677 ns" { receive:inst|LessThan0~534 receive:inst|LessThan0~535 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.150 ns) 3.188 ns receive:inst\|i\[1\]~423 5 COMB LCCOMB_X50_Y24_N0 10 " "Info: 5: + IC(0.540 ns) + CELL(0.150 ns) = 3.188 ns; Loc. = LCCOMB_X50_Y24_N0; Fanout = 10; COMB Node = 'receive:inst\|i\[1\]~423'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.690 ns" { receive:inst|LessThan0~535 receive:inst|i[1]~423 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.248 ns) + CELL(0.393 ns) 3.829 ns receive:inst\|i\[1\]~426 6 COMB LCCOMB_X50_Y24_N2 2 " "Info: 6: + IC(0.248 ns) + CELL(0.393 ns) = 3.829 ns; Loc. = LCCOMB_X50_Y24_N2; Fanout = 2; COMB Node = 'receive:inst\|i\[1\]~426'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.641 ns" { receive:inst|i[1]~423 receive:inst|i[1]~426 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.900 ns receive:inst\|i\[2\]~427 7 COMB LCCOMB_X50_Y24_N4 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 3.900 ns; Loc. = LCCOMB_X50_Y24_N4; Fanout = 2; COMB Node = 'receive:inst\|i\[2\]~427'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[1]~426 receive:inst|i[2]~427 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 3.971 ns receive:inst\|i\[3\]~428 8 COMB LCCOMB_X50_Y24_N6 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 3.971 ns; Loc. = LCCOMB_X50_Y24_N6; Fanout = 2; COMB Node = 'receive:inst\|i\[3\]~428'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[2]~427 receive:inst|i[3]~428 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.042 ns receive:inst\|i\[4\]~429 9 COMB LCCOMB_X50_Y24_N8 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 4.042 ns; Loc. = LCCOMB_X50_Y24_N8; Fanout = 2; COMB Node = 'receive:inst\|i\[4\]~429'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[3]~428 receive:inst|i[4]~429 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.113 ns receive:inst\|i\[5\]~430 10 COMB LCCOMB_X50_Y24_N10 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 4.113 ns; Loc. = LCCOMB_X50_Y24_N10; Fanout = 2; COMB Node = 'receive:inst\|i\[5\]~430'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[4]~429 receive:inst|i[5]~430 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.184 ns receive:inst\|i\[6\]~431 11 COMB LCCOMB_X50_Y24_N12 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 4.184 ns; Loc. = LCCOMB_X50_Y24_N12; Fanout = 2; COMB Node = 'receive:inst\|i\[6\]~431'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[5]~430 receive:inst|i[6]~431 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 4.343 ns receive:inst\|i\[7\]~432 12 COMB LCCOMB_X50_Y24_N14 2 " "Info: 12: + IC(0.000 ns) + CELL(0.159 ns) = 4.343 ns; Loc. = LCCOMB_X50_Y24_N14; Fanout = 2; COMB Node = 'receive:inst\|i\[7\]~432'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { receive:inst|i[6]~431 receive:inst|i[7]~432 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.414 ns receive:inst\|i\[8\]~433 13 COMB LCCOMB_X50_Y24_N16 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 4.414 ns; Loc. = LCCOMB_X50_Y24_N16; Fanout = 2; COMB Node = 'receive:inst\|i\[8\]~433'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[7]~432 receive:inst|i[8]~433 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.485 ns receive:inst\|i\[9\]~434 14 COMB LCCOMB_X50_Y24_N18 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 4.485 ns; Loc. = LCCOMB_X50_Y24_N18; Fanout = 2; COMB Node = 'receive:inst\|i\[9\]~434'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[8]~433 receive:inst|i[9]~434 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.556 ns receive:inst\|i\[10\]~435 15 COMB LCCOMB_X50_Y24_N20 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 4.556 ns; Loc. = LCCOMB_X50_Y24_N20; Fanout = 2; COMB Node = 'receive:inst\|i\[10\]~435'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[9]~434 receive:inst|i[10]~435 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.627 ns receive:inst\|i\[11\]~436 16 COMB LCCOMB_X50_Y24_N22 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 4.627 ns; Loc. = LCCOMB_X50_Y24_N22; Fanout = 2; COMB Node = 'receive:inst\|i\[11\]~436'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[10]~435 receive:inst|i[11]~436 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.698 ns receive:inst\|i\[12\]~437 17 COMB LCCOMB_X50_Y24_N24 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 4.698 ns; Loc. = LCCOMB_X50_Y24_N24; Fanout = 2; COMB Node = 'receive:inst\|i\[12\]~437'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[11]~436 receive:inst|i[12]~437 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.769 ns receive:inst\|i\[13\]~438 18 COMB LCCOMB_X50_Y24_N26 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 4.769 ns; Loc. = LCCOMB_X50_Y24_N26; Fanout = 2; COMB Node = 'receive:inst\|i\[13\]~438'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[12]~437 receive:inst|i[13]~438 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 4.840 ns receive:inst\|i\[14\]~439 19 COMB LCCOMB_X50_Y24_N28 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 4.840 ns; Loc. = LCCOMB_X50_Y24_N28; Fanout = 2; COMB Node = 'receive:inst\|i\[14\]~439'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[13]~438 receive:inst|i[14]~439 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 4.986 ns receive:inst\|i\[15\]~440 20 COMB LCCOMB_X50_Y24_N30 2 " "Info: 20: + IC(0.000 ns) + CELL(0.146 ns) = 4.986 ns; Loc. = LCCOMB_X50_Y24_N30; Fanout = 2; COMB Node = 'receive:inst\|i\[15\]~440'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.146 ns" { receive:inst|i[14]~439 receive:inst|i[15]~440 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.057 ns receive:inst\|i\[16\]~441 21 COMB LCCOMB_X50_Y23_N0 2 " "Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 5.057 ns; Loc. = LCCOMB_X50_Y23_N0; Fanout = 2; COMB Node = 'receive:inst\|i\[16\]~441'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[15]~440 receive:inst|i[16]~441 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.128 ns receive:inst\|i\[17\]~442 22 COMB LCCOMB_X50_Y23_N2 2 " "Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 5.128 ns; Loc. = LCCOMB_X50_Y23_N2; Fanout = 2; COMB Node = 'receive:inst\|i\[17\]~442'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[16]~441 receive:inst|i[17]~442 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.199 ns receive:inst\|i\[18\]~443 23 COMB LCCOMB_X50_Y23_N4 2 " "Info: 23: + IC(0.000 ns) + CELL(0.071 ns) = 5.199 ns; Loc. = LCCOMB_X50_Y23_N4; Fanout = 2; COMB Node = 'receive:inst\|i\[18\]~443'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[17]~442 receive:inst|i[18]~443 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.270 ns receive:inst\|i\[19\]~444 24 COMB LCCOMB_X50_Y23_N6 2 " "Info: 24: + IC(0.000 ns) + CELL(0.071 ns) = 5.270 ns; Loc. = LCCOMB_X50_Y23_N6; Fanout = 2; COMB Node = 'receive:inst\|i\[19\]~444'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[18]~443 receive:inst|i[19]~444 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.341 ns receive:inst\|i\[20\]~445 25 COMB LCCOMB_X50_Y23_N8 2 " "Info: 25: + IC(0.000 ns) + CELL(0.071 ns) = 5.341 ns; Loc. = LCCOMB_X50_Y23_N8; Fanout = 2; COMB Node = 'receive:inst\|i\[20\]~445'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[19]~444 receive:inst|i[20]~445 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.412 ns receive:inst\|i\[21\]~446 26 COMB LCCOMB_X50_Y23_N10 2 " "Info: 26: + IC(0.000 ns) + CELL(0.071 ns) = 5.412 ns; Loc. = LCCOMB_X50_Y23_N10; Fanout = 2; COMB Node = 'receive:inst\|i\[21\]~446'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[20]~445 receive:inst|i[21]~446 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.483 ns receive:inst\|i\[22\]~447 27 COMB LCCOMB_X50_Y23_N12 2 " "Info: 27: + IC(0.000 ns) + CELL(0.071 ns) = 5.483 ns; Loc. = LCCOMB_X50_Y23_N12; Fanout = 2; COMB Node = 'receive:inst\|i\[22\]~447'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[21]~446 receive:inst|i[22]~447 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 5.642 ns receive:inst\|i\[23\]~448 28 COMB LCCOMB_X50_Y23_N14 2 " "Info: 28: + IC(0.000 ns) + CELL(0.159 ns) = 5.642 ns; Loc. = LCCOMB_X50_Y23_N14; Fanout = 2; COMB Node = 'receive:inst\|i\[23\]~448'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { receive:inst|i[22]~447 receive:inst|i[23]~448 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.713 ns receive:inst\|i\[24\]~449 29 COMB LCCOMB_X50_Y23_N16 2 " "Info: 29: + IC(0.000 ns) + CELL(0.071 ns) = 5.713 ns; Loc. = LCCOMB_X50_Y23_N16; Fanout = 2; COMB Node = 'receive:inst\|i\[24\]~449'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[23]~448 receive:inst|i[24]~449 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.784 ns receive:inst\|i\[25\]~450 30 COMB LCCOMB_X50_Y23_N18 2 " "Info: 30: + IC(0.000 ns) + CELL(0.071 ns) = 5.784 ns; Loc. = LCCOMB_X50_Y23_N18; Fanout = 2; COMB Node = 'receive:inst\|i\[25\]~450'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[24]~449 receive:inst|i[25]~450 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.855 ns receive:inst\|i\[26\]~451 31 COMB LCCOMB_X50_Y23_N20 2 " "Info: 31: + IC(0.000 ns) + CELL(0.071 ns) = 5.855 ns; Loc. = LCCOMB_X50_Y23_N20; Fanout = 2; COMB Node = 'receive:inst\|i\[26\]~451'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[25]~450 receive:inst|i[26]~451 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.926 ns receive:inst\|i\[27\]~452 32 COMB LCCOMB_X50_Y23_N22 2 " "Info: 32: + IC(0.000 ns) + CELL(0.071 ns) = 5.926 ns; Loc. = LCCOMB_X50_Y23_N22; Fanout = 2; COMB Node = 'receive:inst\|i\[27\]~452'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[26]~451 receive:inst|i[27]~452 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 5.997 ns receive:inst\|i\[28\]~453 33 COMB LCCOMB_X50_Y23_N24 2 " "Info: 33: + IC(0.000 ns) + CELL(0.071 ns) = 5.997 ns; Loc. = LCCOMB_X50_Y23_N24; Fanout = 2; COMB Node = 'receive:inst\|i\[28\]~453'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[27]~452 receive:inst|i[28]~453 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 6.068 ns receive:inst\|i\[29\]~454 34 COMB LCCOMB_X50_Y23_N26 2 " "Info: 34: + IC(0.000 ns) + CELL(0.071 ns) = 6.068 ns; Loc. = LCCOMB_X50_Y23_N26; Fanout = 2; COMB Node = 'receive:inst\|i\[29\]~454'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[28]~453 receive:inst|i[29]~454 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 6.139 ns receive:inst\|i\[30\]~455 35 COMB LCCOMB_X50_Y23_N28 1 " "Info: 35: + IC(0.000 ns) + CELL(0.071 ns) = 6.139 ns; Loc. = LCCOMB_X50_Y23_N28; Fanout = 1; COMB Node = 'receive:inst\|i\[30\]~455'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { receive:inst|i[29]~454 receive:inst|i[30]~455 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 6.549 ns receive:inst\|i\[31\]~253 36 COMB LCCOMB_X50_Y23_N30 1 " "Info: 36: + IC(0.000 ns) + CELL(0.410 ns) = 6.549 ns; Loc. = LCCOMB_X50_Y23_N30; Fanout = 1; COMB Node = 'receive:inst\|i\[31\]~253'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { receive:inst|i[30]~455 receive:inst|i[31]~253 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.633 ns receive:inst\|i\[31\] 37 REG LCFF_X50_Y23_N31 8 " "Info: 37: + IC(0.000 ns) + CELL(0.084 ns) = 6.633 ns; Loc. = LCFF_X50_Y23_N31; Fanout = 8; REG Node = 'receive:inst\|i\[31\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { receive:inst|i[31]~253 receive:inst|i[31] } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.288 ns ( 64.65 % ) " "Info: Total cell delay = 4.288 ns ( 64.65 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.345 ns ( 35.35 % ) " "Info: Total interconnect delay = 2.345 ns ( 35.35 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.633 ns" { receive:inst|i[26] receive:inst|LessThan0~533 receive:inst|LessThan0~534 receive:inst|LessThan0~535 receive:inst|i[1]~423 receive:inst|i[1]~426 receive:inst|i[2]~427 receive:inst|i[3]~428 receive:inst|i[4]~429 receive:inst|i[5]~430 receive:inst|i[6]~431 receive:inst|i[7]~432 receive:inst|i[8]~433 receive:inst|i[9]~434 receive:inst|i[10]~435 receive:inst|i[11]~436 receive:inst|i[12]~437 receive:inst|i[13]~438 receive:inst|i[14]~439 receive:inst|i[15]~440 receive:inst|i[16]~441 receive:inst|i[17]~442 receive:inst|i[18]~443 receive:inst|i[19]~444 receive:inst|i[20]~445 receive:inst|i[21]~446 receive:inst|i[22]~447 receive:inst|i[23]~448 receive:inst|i[24]~449 receive:inst|i[25]~450 receive:inst|i[26]~451 receive:inst|i[27]~452 receive:inst|i[28]~453 receive:inst|i[29]~454 receive:inst|i[30]~455 receive:inst|i[31]~253 receive:inst|i[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.633 ns" { receive:inst|i[26] receive:inst|LessThan0~533 receive:inst|LessThan0~534 receive:inst|LessThan0~535 receive:inst|i[1]~423 receive:inst|i[1]~426 receive:inst|i[2]~427 receive:inst|i[3]~428 receive:inst|i[4]~429 receive:inst|i[5]~430 receive:inst|i[6]~431 receive:inst|i[7]~432 receive:inst|i[8]~433 receive:inst|i[9]~434 receive:inst|i[10]~435 receive:inst|i[11]~436 receive:inst|i[12]~437 receive:inst|i[13]~438 receive:inst|i[14]~439 receive:inst|i[15]~440 receive:inst|i[16]~441 receive:inst|i[17]~442 receive:inst|i[18]~443 receive:inst|i[19]~444 receive:inst|i[20]~445 receive:inst|i[21]~446 receive:inst|i[22]~447 receive:inst|i[23]~448 receive:inst|i[24]~449 receive:inst|i[25]~450 receive:inst|i[26]~451 receive:inst|i[27]~452 receive:inst|i[28]~453 receive:inst|i[29]~454 receive:inst|i[30]~455 receive:inst|i[31]~253 receive:inst|i[31] } { 0.000ns 1.035ns 0.265ns 0.257ns 0.540ns 0.248ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.371ns 0.150ns 0.420ns 0.150ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.142 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.872 ns) 0.872 ns clk 1 CLK PIN_D26 41 " "Info: 1: + IC(0.000 ns) + CELL(0.872 ns) = 0.872 ns; Loc. = PIN_D26; Fanout = 41; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "show.bdf" "" { Schematic "D:/alter/show/show.bdf" { { 184 24 192 200 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.733 ns) + CELL(0.537 ns) 3.142 ns receive:inst\|i\[31\] 2 REG LCFF_X50_Y23_N31 8 " "Info: 2: + IC(1.733 ns) + CELL(0.537 ns) = 3.142 ns; Loc. = LCFF_X50_Y23_N31; Fanout = 8; REG Node = 'receive:inst\|i\[31\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.270 ns" { clk receive:inst|i[31] } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.409 ns ( 44.84 % ) " "Info: Total cell delay = 1.409 ns ( 44.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.733 ns ( 55.16 % ) " "Info: Total interconnect delay = 1.733 ns ( 55.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.142 ns" { clk receive:inst|i[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.142 ns" { clk clk~combout receive:inst|i[31] } { 0.000ns 0.000ns 1.733ns } { 0.000ns 0.872ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.142 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.142 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.872 ns) 0.872 ns clk 1 CLK PIN_D26 41 " "Info: 1: + IC(0.000 ns) + CELL(0.872 ns) = 0.872 ns; Loc. = PIN_D26; Fanout = 41; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "show.bdf" "" { Schematic "D:/alter/show/show.bdf" { { 184 24 192 200 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.733 ns) + CELL(0.537 ns) 3.142 ns receive:inst\|i\[26\] 2 REG LCFF_X50_Y23_N21 3 " "Info: 2: + IC(1.733 ns) + CELL(0.537 ns) = 3.142 ns; Loc. = LCFF_X50_Y23_N21; Fanout = 3; REG Node = 'receive:inst\|i\[26\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.270 ns" { clk receive:inst|i[26] } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.409 ns ( 44.84 % ) " "Info: Total cell delay = 1.409 ns ( 44.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.733 ns ( 55.16 % ) " "Info: Total interconnect delay = 1.733 ns ( 55.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.142 ns" { clk receive:inst|i[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.142 ns" { clk clk~combout receive:inst|i[26] } { 0.000ns 0.000ns 1.733ns } { 0.000ns 0.872ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.142 ns" { clk receive:inst|i[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.142 ns" { clk clk~combout receive:inst|i[31] } { 0.000ns 0.000ns 1.733ns } { 0.000ns 0.872ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.142 ns" { clk receive:inst|i[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.142 ns" { clk clk~combout receive:inst|i[26] } { 0.000ns 0.000ns 1.733ns } { 0.000ns 0.872ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.633 ns" { receive:inst|i[26] receive:inst|LessThan0~533 receive:inst|LessThan0~534 receive:inst|LessThan0~535 receive:inst|i[1]~423 receive:inst|i[1]~426 receive:inst|i[2]~427 receive:inst|i[3]~428 receive:inst|i[4]~429 receive:inst|i[5]~430 receive:inst|i[6]~431 receive:inst|i[7]~432 receive:inst|i[8]~433 receive:inst|i[9]~434 receive:inst|i[10]~435 receive:inst|i[11]~436 receive:inst|i[12]~437 receive:inst|i[13]~438 receive:inst|i[14]~439 receive:inst|i[15]~440 receive:inst|i[16]~441 receive:inst|i[17]~442 receive:inst|i[18]~443 receive:inst|i[19]~444 receive:inst|i[20]~445 receive:inst|i[21]~446 receive:inst|i[22]~447 receive:inst|i[23]~448 receive:inst|i[24]~449 receive:inst|i[25]~450 receive:inst|i[26]~451 receive:inst|i[27]~452 receive:inst|i[28]~453 receive:inst|i[29]~454 receive:inst|i[30]~455 receive:inst|i[31]~253 receive:inst|i[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.633 ns" { receive:inst|i[26] receive:inst|LessThan0~533 receive:inst|LessThan0~534 receive:inst|LessThan0~535 receive:inst|i[1]~423 receive:inst|i[1]~426 receive:inst|i[2]~427 receive:inst|i[3]~428 receive:inst|i[4]~429 receive:inst|i[5]~430 receive:inst|i[6]~431 receive:inst|i[7]~432 receive:inst|i[8]~433 receive:inst|i[9]~434 receive:inst|i[10]~435 receive:inst|i[11]~436 receive:inst|i[12]~437 receive:inst|i[13]~438 receive:inst|i[14]~439 receive:inst|i[15]~440 receive:inst|i[16]~441 receive:inst|i[17]~442 receive:inst|i[18]~443 receive:inst|i[19]~444 receive:inst|i[20]~445 receive:inst|i[21]~446 receive:inst|i[22]~447 receive:inst|i[23]~448 receive:inst|i[24]~449 receive:inst|i[25]~450 receive:inst|i[26]~451 receive:inst|i[27]~452 receive:inst|i[28]~453 receive:inst|i[29]~454 receive:inst|i[30]~455 receive:inst|i[31]~253 receive:inst|i[31] } { 0.000ns 1.035ns 0.265ns 0.257ns 0.540ns 0.248ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.371ns 0.150ns 0.420ns 0.150ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.142 ns" { clk receive:inst|i[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.142 ns" { clk clk~combout receive:inst|i[31] } { 0.000ns 0.000ns 1.733ns } { 0.000ns 0.872ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.142 ns" { clk receive:inst|i[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.142 ns" { clk clk~combout receive:inst|i[26] } { 0.000ns 0.000ns 1.733ns } { 0.000ns 0.872ns 0.537ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "receive:inst\|dat_out\[2\] receive:inst\|b8 clk 2.711 ns " "Info: Found hold time violation between source pin or register \"receive:inst\|dat_out\[2\]\" and destination pin or register \"receive:inst\|b8\" for clock \"clk\" (Hold time is 2.711 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.691 ns + Largest " "Info: + Largest clock skew is 3.691 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.797 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.797 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.872 ns) 0.872 ns clk 1 CLK PIN_D26 41 " "Info: 1: + IC(0.000 ns) + CELL(0.872 ns) = 0.872 ns; Loc. = PIN_D26; Fanout = 41; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "show.bdf" "" { Schematic "D:/alter/show/show.bdf" { { 184 24 192 200 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.711 ns) + CELL(0.787 ns) 3.370 ns receive:inst\|temp 2 REG LCFF_X50_Y25_N19 2 " "Info: 2: + IC(1.711 ns) + CELL(0.787 ns) = 3.370 ns; Loc. = LCFF_X50_Y25_N19; Fanout = 2; REG Node = 'receive:inst\|temp'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.498 ns" { clk receive:inst|temp } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.816 ns) + CELL(0.000 ns) 5.186 ns receive:inst\|temp~clkctrl 3 COMB CLKCTRL_G6 8 " "Info: 3: + IC(1.816 ns) + CELL(0.000 ns) = 5.186 ns; Loc. = CLKCTRL_G6; Fanout = 8; COMB Node = 'receive:inst\|temp~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.816 ns" { receive:inst|temp receive:inst|temp~clkctrl } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.336 ns) + CELL(0.275 ns) 6.797 ns receive:inst\|b8 4 REG LCCOMB_X53_Y24_N26 6 " "Info: 4: + IC(1.336 ns) + CELL(0.275 ns) = 6.797 ns; Loc. = LCCOMB_X53_Y24_N26; Fanout = 6; REG Node = 'receive:inst\|b8'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.611 ns" { receive:inst|temp~clkctrl receive:inst|b8 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.934 ns ( 28.45 % ) " "Info: Total cell delay = 1.934 ns ( 28.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.863 ns ( 71.55 % ) " "Info: Total interconnect delay = 4.863 ns ( 71.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.797 ns" { clk receive:inst|temp receive:inst|temp~clkctrl receive:inst|b8 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.797 ns" { clk clk~combout receive:inst|temp receive:inst|temp~clkctrl receive:inst|b8 } { 0.000ns 0.000ns 1.711ns 1.816ns 1.336ns } { 0.000ns 0.872ns 0.787ns 0.000ns 0.275ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.106 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.106 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.872 ns) 0.872 ns clk 1 CLK PIN_D26 41 " "Info: 1: + IC(0.000 ns) + CELL(0.872 ns) = 0.872 ns; Loc. = PIN_D26; Fanout = 41; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "show.bdf" "" { Schematic "D:/alter/show/show.bdf" { { 184 24 192 200 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.697 ns) + CELL(0.537 ns) 3.106 ns receive:inst\|dat_out\[2\] 2 REG LCFF_X53_Y24_N19 2 " "Info: 2: + IC(1.697 ns) + CELL(0.537 ns) = 3.106 ns; Loc. = LCFF_X53_Y24_N19; Fanout = 2; REG Node = 'receive:inst\|dat_out\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.234 ns" { clk receive:inst|dat_out[2] } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.409 ns ( 45.36 % ) " "Info: Total cell delay = 1.409 ns ( 45.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.697 ns ( 54.64 % ) " "Info: Total interconnect delay = 1.697 ns ( 54.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.106 ns" { clk receive:inst|dat_out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.106 ns" { clk clk~combout receive:inst|dat_out[2] } { 0.000ns 0.000ns 1.697ns } { 0.000ns 0.872ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.797 ns" { clk receive:inst|temp receive:inst|temp~clkctrl receive:inst|b8 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.797 ns" { clk clk~combout receive:inst|temp receive:inst|temp~clkctrl receive:inst|b8 } { 0.000ns 0.000ns 1.711ns 1.816ns 1.336ns } { 0.000ns 0.872ns 0.787ns 0.000ns 0.275ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.106 ns" { clk receive:inst|dat_out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.106 ns" { clk clk~combout receive:inst|dat_out[2] } { 0.000ns 0.000ns 1.697ns } { 0.000ns 0.872ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.730 ns - Shortest register register " "Info: - Shortest register to register delay is 0.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns receive:inst\|dat_out\[2\] 1 REG LCFF_X53_Y24_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X53_Y24_N19; Fanout = 2; REG Node = 'receive:inst\|dat_out\[2\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { receive:inst|dat_out[2] } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.311 ns) + CELL(0.419 ns) 0.730 ns receive:inst\|b8 2 REG LCCOMB_X53_Y24_N26 6 " "Info: 2: + IC(0.311 ns) + CELL(0.419 ns) = 0.730 ns; Loc. = LCCOMB_X53_Y24_N26; Fanout = 6; REG Node = 'receive:inst\|b8'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.730 ns" { receive:inst|dat_out[2] receive:inst|b8 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.419 ns ( 57.40 % ) " "Info: Total cell delay = 0.419 ns ( 57.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.311 ns ( 42.60 % ) " "Info: Total interconnect delay = 0.311 ns ( 42.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.730 ns" { receive:inst|dat_out[2] receive:inst|b8 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.730 ns" { receive:inst|dat_out[2] receive:inst|b8 } { 0.000ns 0.311ns } { 0.000ns 0.419ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" { } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 10 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 10 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.797 ns" { clk receive:inst|temp receive:inst|temp~clkctrl receive:inst|b8 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.797 ns" { clk clk~combout receive:inst|temp receive:inst|temp~clkctrl receive:inst|b8 } { 0.000ns 0.000ns 1.711ns 1.816ns 1.336ns } { 0.000ns 0.872ns 0.787ns 0.000ns 0.275ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.106 ns" { clk receive:inst|dat_out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.106 ns" { clk clk~combout receive:inst|dat_out[2] } { 0.000ns 0.000ns 1.697ns } { 0.000ns 0.872ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.730 ns" { receive:inst|dat_out[2] receive:inst|b8 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.730 ns" { receive:inst|dat_out[2] receive:inst|b8 } { 0.000ns 0.311ns } { 0.000ns 0.419ns } } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
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