{ "Info" "ITDB_TSU_RESULT" "receive:inst\|dat_out\[8\] dat clk 4.692 ns register " "Info: tsu for register \"receive:inst\|dat_out\[8\]\" (data pin = \"dat\", clock pin = \"clk\") is 4.692 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.834 ns + Longest pin register " "Info: + Longest pin to register delay is 7.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.882 ns) 0.882 ns dat 1 PIN PIN_C24 9 " "Info: 1: + IC(0.000 ns) + CELL(0.882 ns) = 0.882 ns; Loc. = PIN_C24; Fanout = 9; PIN Node = 'dat'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dat } "NODE_NAME" } } { "show.bdf" "" { Schematic "D:/alter/show/show.bdf" { { 200 24 192 216 "dat" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.449 ns) + CELL(0.419 ns) 7.750 ns receive:inst\|dat_out\[8\]~61 2 COMB LCCOMB_X53_Y24_N6 1 " "Info: 2: + IC(6.449 ns) + CELL(0.419 ns) = 7.750 ns; Loc. = LCCOMB_X53_Y24_N6; Fanout = 1; COMB Node = 'receive:inst\|dat_out\[8\]~61'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.868 ns" { dat receive:inst|dat_out[8]~61 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 7.834 ns receive:inst\|dat_out\[8\] 3 REG LCFF_X53_Y24_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 7.834 ns; Loc. = LCFF_X53_Y24_N7; Fanout = 2; REG Node = 'receive:inst\|dat_out\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { receive:inst|dat_out[8]~61 receive:inst|dat_out[8] } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.385 ns ( 17.68 % ) " "Info: Total cell delay = 1.385 ns ( 17.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.449 ns ( 82.32 % ) " "Info: Total interconnect delay = 6.449 ns ( 82.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.834 ns" { dat receive:inst|dat_out[8]~61 receive:inst|dat_out[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.834 ns" { dat dat~combout receive:inst|dat_out[8]~61 receive:inst|dat_out[8] } { 0.000ns 0.000ns 6.449ns 0.000ns } { 0.000ns 0.882ns 0.419ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.106 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.106 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.872 ns) 0.872 ns clk 1 CLK PIN_D26 41 " "Info: 1: + IC(0.000 ns) + CELL(0.872 ns) = 0.872 ns; Loc. = PIN_D26; Fanout = 41; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "show.bdf" "" { Schematic "D:/alter/show/show.bdf" { { 184 24 192 200 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.697 ns) + CELL(0.537 ns) 3.106 ns receive:inst\|dat_out\[8\] 2 REG LCFF_X53_Y24_N7 2 " "Info: 2: + IC(1.697 ns) + CELL(0.537 ns) = 3.106 ns; Loc. = LCFF_X53_Y24_N7; Fanout = 2; REG Node = 'receive:inst\|dat_out\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.234 ns" { clk receive:inst|dat_out[8] } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.409 ns ( 45.36 % ) " "Info: Total cell delay = 1.409 ns ( 45.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.697 ns ( 54.64 % ) " "Info: Total interconnect delay = 1.697 ns ( 54.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.106 ns" { clk receive:inst|dat_out[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.106 ns" { clk clk~combout receive:inst|dat_out[8] } { 0.000ns 0.000ns 1.697ns } { 0.000ns 0.872ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.834 ns" { dat receive:inst|dat_out[8]~61 receive:inst|dat_out[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.834 ns" { dat dat~combout receive:inst|dat_out[8]~61 receive:inst|dat_out[8] } { 0.000ns 0.000ns 6.449ns 0.000ns } { 0.000ns 0.882ns 0.419ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.106 ns" { clk receive:inst|dat_out[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.106 ns" { clk clk~combout receive:inst|dat_out[8] } { 0.000ns 0.000ns 1.697ns } { 0.000ns 0.872ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk c receive:inst\|b2 17.308 ns register " "Info: tco from clock \"clk\" to destination pin \"c\" through register \"receive:inst\|b2\" is 17.308 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.687 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.687 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.872 ns) 0.872 ns clk 1 CLK PIN_D26 41 " "Info: 1: + IC(0.000 ns) + CELL(0.872 ns) = 0.872 ns; Loc. = PIN_D26; Fanout = 41; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "show.bdf" "" { Schematic "D:/alter/show/show.bdf" { { 184 24 192 200 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.711 ns) + CELL(0.787 ns) 3.370 ns receive:inst\|temp 2 REG LCFF_X50_Y25_N19 2 " "Info: 2: + IC(1.711 ns) + CELL(0.787 ns) = 3.370 ns; Loc. = LCFF_X50_Y25_N19; Fanout = 2; REG Node = 'receive:inst\|temp'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.498 ns" { clk receive:inst|temp } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.816 ns) + CELL(0.000 ns) 5.186 ns receive:inst\|temp~clkctrl 3 COMB CLKCTRL_G6 8 " "Info: 3: + IC(1.816 ns) + CELL(0.000 ns) = 5.186 ns; Loc. = CLKCTRL_G6; Fanout = 8; COMB Node = 'receive:inst\|temp~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.816 ns" { receive:inst|temp receive:inst|temp~clkctrl } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.351 ns) + CELL(0.150 ns) 6.687 ns receive:inst\|b2 4 REG LCCOMB_X53_Y24_N4 11 " "Info: 4: + IC(1.351 ns) + CELL(0.150 ns) = 6.687 ns; Loc. = LCCOMB_X53_Y24_N4; Fanout = 11; REG Node = 'receive:inst\|b2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.501 ns" { receive:inst|temp~clkctrl receive:inst|b2 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.809 ns ( 27.05 % ) " "Info: Total cell delay = 1.809 ns ( 27.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.878 ns ( 72.95 % ) " "Info: Total interconnect delay = 4.878 ns ( 72.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.687 ns" { clk receive:inst|temp receive:inst|temp~clkctrl receive:inst|b2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.687 ns" { clk clk~combout receive:inst|temp receive:inst|temp~clkctrl receive:inst|b2 } { 0.000ns 0.000ns 1.711ns 1.816ns 1.351ns } { 0.000ns 0.872ns 0.787ns 0.000ns 0.150ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.621 ns + Longest register pin " "Info: + Longest register to pin delay is 10.621 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns receive:inst\|b2 1 REG LCCOMB_X53_Y24_N4 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X53_Y24_N4; Fanout = 11; REG Node = 'receive:inst\|b2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { receive:inst|b2 } "NODE_NAME" } } { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(0.438 ns) 1.815 ns seg_decode:inst6\|Mux4~718 2 COMB LCCOMB_X50_Y22_N10 2 " "Info: 2: + IC(1.377 ns) + CELL(0.438 ns) = 1.815 ns; Loc. = LCCOMB_X50_Y22_N10; Fanout = 2; COMB Node = 'seg_decode:inst6\|Mux4~718'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.815 ns" { receive:inst|b2 seg_decode:inst6|Mux4~718 } "NODE_NAME" } } { "seg_decode.vhd" "" { Text "D:/alter/show/seg_decode.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.764 ns) + CELL(0.419 ns) 2.998 ns seg_decode:inst6\|Mux4~719 3 COMB LCCOMB_X50_Y25_N10 1 " "Info: 3: + IC(0.764 ns) + CELL(0.419 ns) = 2.998 ns; Loc. = LCCOMB_X50_Y25_N10; Fanout = 1; COMB Node = 'seg_decode:inst6\|Mux4~719'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.183 ns" { seg_decode:inst6|Mux4~718 seg_decode:inst6|Mux4~719 } "NODE_NAME" } } { "seg_decode.vhd" "" { Text "D:/alter/show/seg_decode.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.744 ns) + CELL(0.420 ns) 4.162 ns seg_decode:inst6\|Mux4~720 4 COMB LCCOMB_X50_Y22_N24 1 " "Info: 4: + IC(0.744 ns) + CELL(0.420 ns) = 4.162 ns; Loc. = LCCOMB_X50_Y22_N24; Fanout = 1; COMB Node = 'seg_decode:inst6\|Mux4~720'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.164 ns" { seg_decode:inst6|Mux4~719 seg_decode:inst6|Mux4~720 } "NODE_NAME" } } { "seg_decode.vhd" "" { Text "D:/alter/show/seg_decode.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.681 ns) + CELL(2.778 ns) 10.621 ns c 5 PIN PIN_AC12 0 " "Info: 5: + IC(3.681 ns) + CELL(2.778 ns) = 10.621 ns; Loc. = PIN_AC12; Fanout = 0; PIN Node = 'c'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.459 ns" { seg_decode:inst6|Mux4~720 c } "NODE_NAME" } } { "show.bdf" "" { Schematic "D:/alter/show/show.bdf" { { 216 472 648 232 "c" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.055 ns ( 38.18 % ) " "Info: Total cell delay = 4.055 ns ( 38.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.566 ns ( 61.82 % ) " "Info: Total in