{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 13 18:35:13 2007 " "Info: Processing started: Tue Nov 13 18:35:13 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off show -c show " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off show -c show" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg_decode.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg_decode.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg_decode-seg_decode_arch " "Info: Found design unit 1: seg_decode-seg_decode_arch" {  } { { "seg_decode.vhd" "" { Text "D:/alter/show/seg_decode.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seg_decode " "Info: Found entity 1: seg_decode" {  } { { "seg_decode.vhd" "" { Text "D:/alter/show/seg_decode.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "receive.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file receive.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 receive-receive_arth " "Info: Found design unit 1: receive-receive_arth" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 receive " "Info: Found entity 1: receive" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/alter/show/show2.vhd " "Warning: Can't analyze file -- file D:/alter/show/show2.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "show.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file show.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 show " "Info: Found entity 1: show" {  } { { "show.bdf" "" { Schematic "D:/alter/show/show.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "show " "Info: Elaborating entity \"show\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seg_decode seg_decode:inst6 " "Info: Elaborating entity \"seg_decode\" for hierarchy \"seg_decode:inst6\"" {  } { { "show.bdf" "inst6" { Schematic "D:/alter/show/show.bdf" { { 160 344 440 352 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "receive receive:inst " "Info: Elaborating entity \"receive\" for hierarchy \"receive:inst\"" {  } { { "show.bdf" "inst" { Schematic "D:/alter/show/show.bdf" { { 160 216 312 352 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b1 receive.vhd(16) " "Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable \"b1\", which holds its previous value in one or more paths through the process" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b2 receive.vhd(16) " "Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable \"b2\", which holds its previous value in one or more paths through the process" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b3 receive.vhd(16) " "Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable \"b3\", which holds its previous value in one or more paths through the process" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b4 receive.vhd(16) " "Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable \"b4\", which holds its previous value in one or more paths through the process" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b5 receive.vhd(16) " "Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable \"b5\", which holds its previous value in one or more paths through the process" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b6 receive.vhd(16) " "Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable \"b6\", which holds its previous value in one or more paths through the process" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b7 receive.vhd(16) " "Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable \"b7\", which holds its previous value in one or more paths through the process" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "b8 receive.vhd(16) " "Warning (10631): VHDL Process Statement warning at receive.vhd(16): inferring latch(es) for signal or variable \"b8\", which holds its previous value in one or more paths through the process" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b8 receive.vhd(16) " "Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for \"b8\"" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b7 receive.vhd(16) " "Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for \"b7\"" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b6 receive.vhd(16) " "Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for \"b6\"" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b5 receive.vhd(16) " "Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for \"b5\"" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b4 receive.vhd(16) " "Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for \"b4\"" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b3 receive.vhd(16) " "Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for \"b3\"" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b2 receive.vhd(16) " "Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for \"b2\"" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "b1 receive.vhd(16) " "Info (10041): Verilog HDL or VHDL info at receive.vhd(16): inferred latch for \"b1\"" {  } { { "receive.vhd" "" { Text "D:/alter/show/receive.vhd" 16 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "112 " "Info: Implemented 112 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "103 " "Info: Implemented 103 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 13 18:35:18 2007 " "Info: Processing ended: Tue Nov 13 18:35:18 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}