LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY receive IS
       PORT(
            clk                       : IN  std_logic;
            dat                       : IN  std_logic;
            b1,b2,b3,b4,b5,b6,b7,b8   : OUT std_logic
            );
END receive;

ARCHITECTURE receive_arth OF receive IS
BEGIN
PROCESS (clk,dat)
	VARIABLE dat_out	:	STD_LOGIC_VECTOR(10 DOWNTO 0);
	VARIABLE i          :   integer := 0;
	VARIABLE temp       :   STD_LOGIC :='0';
BEGIN
    IF(clk ='1' AND clk'EVENT) THEN
         dat_out(10-i) := dat;
         temp := temp XOR dat;
         i := i+1;
    END IF;
    IF(i >=11) THEN
    i := 0;
    END IF;
    IF(temp ='1') THEN
    b1 <= dat_out(9);
    b2 <= dat_out(8);
    b3 <= dat_out(7);
    b4 <= dat_out(6);   
    b5 <= dat_out(5); 
    b6 <= dat_out(4);
    b7 <= dat_out(3);
    b8 <= dat_out(2);
    END IF;
END PROCESS;
END receive_arth;