?? plback_adv7179.v
字號:
dac_cmd_enb_odd <= 0;
end
else
begin
dac_cmd_enb_odd <= mpu_cmd_grant;
end
end
always @(posedge sys_clk)
begin
if(sys_rstn==1'b0)
begin
time_cnt <= 0;
end
else if(((state==st_rd_luma)|(state==st_rd_chroma_u)|(state==st_rd_chroma_v)) & (~mpu_cmd_vld))
begin
time_cnt <= time_cnt + 1;
end
else
begin
time_cnt <= 0;
end
end
always @(posedge sys_clk)
begin
if(sys_rstn==1'b0)
fill_luma_over <= 1'b0;
else if(((state == st_rd_luma)&(fill_cnt==10'd720)& ( ~fill_odd_even)) |timeout)
fill_luma_over <= 1'b1;
else
fill_luma_over <= 1'b0;
end
always @(posedge sys_clk)
begin
if(sys_rstn==1'b0)
fill_chroma_u_over <= 1'b0;
else if(((state == st_rd_chroma_u)&(fill_cnt==10'd360)&(pass_chroma_cnt[0]==1'b0))& ( ~fill_odd_even) |
((state==st_rd_chroma_u) & (pass_chroma_cnt[0] ==1'b1))& ( ~fill_odd_even) | timeout)
fill_chroma_u_over <= 1'b1;
else
fill_chroma_u_over <= 1'b0;
end
always @(posedge sys_clk)
begin
if(sys_rstn==1'b0)
fill_chroma_v_over <= 1'b0;
else if(((state == st_rd_chroma_v)&(fill_cnt==10'd360)&(pass_chroma_cnt[0]==1'b0))& ( ~fill_odd_even)|
((state==st_rd_chroma_v) & (pass_chroma_cnt[0] ==1'b1))& ( ~fill_odd_even)| timeout)
fill_chroma_v_over <= 1'b1;
else
fill_chroma_v_over <= 1'b0;
end
//cross clock domain
always @(posedge sys_clk)
begin
rd_buf_flag_d <= rd_buf_flag;
rd_buf_flag <= rd_buf_flag_p;
rd_buf_flag_p <= rd_buf_flag_dac;
end
always @(posedge sys_clk)
begin
if(sys_rstn==1'b0)
begin
dpr_wr_data <= 0;
dpr_wr_lu0_data <= 0;
dpr_wr_lu1_data <= 0;
end
else
begin
if( fill_odd_even==1'b0 )
begin
if(state==st_rd_luma)
begin
dpr_wr_lu0_data[15:0] <= mpu_cmd_data[31:16];
dpr_wr_lu1_data[15:0] <= mpu_cmd_data[15:0];
end
else
begin
dpr_wr_data <= mpu_cmd_data;
end
end
else
begin
if (de_out_luma_enb )
begin
dpr_wr_lu0_data[15:0] <= de_out_lu_data[31:16];
dpr_wr_lu1_data[15:0] <= de_out_lu_data[15:0];
end
else if ( de_out_u_enb )
begin
dpr_wr_data <= de_out_u_data;
end
else if ( de_out_v_enb )
begin
dpr_wr_data <= de_out_v_data;
end
end
end
end
always @(posedge sys_clk)
begin
if(sys_rstn==1'b0)
begin
dpr_wr_luma0_addr <= 0;
dpr_wr_luma1_addr <= 0;
dpr_wr_luma_enb0 <= 0;
dpr_wr_luma_enb1 <= 0;
dpr_wr_luma_enb2 <= 0;
dpr_wr_luma_enb3 <= 0;
end
else
begin
if ( fill_odd_even == 1'b0 )
begin
dpr_wr_luma_enb0 <= mpu_cmd_vld & ~fill_buf01 &(state==st_rd_luma) ;
dpr_wr_luma_enb1 <= mpu_cmd_vld & ~fill_buf01 &(state==st_rd_luma) ;
dpr_wr_luma_enb2 <= mpu_cmd_vld & fill_buf01 &(state==st_rd_luma) ;
dpr_wr_luma_enb3 <= mpu_cmd_vld & fill_buf01 & (state==st_rd_luma);
if(state == st_rd_luma)
begin
if(dpr_wr_luma_enb0 | dpr_wr_luma_enb1 | dpr_wr_luma_enb2 | dpr_wr_luma_enb3 )
begin
dpr_wr_luma0_addr <= dpr_wr_luma0_addr + 1;
dpr_wr_luma1_addr <= dpr_wr_luma1_addr + 1;
end
end
else
begin
dpr_wr_luma0_addr <= 0;
dpr_wr_luma1_addr <= 0;
end
end
else
if( de_out_luma_enb )
begin
dpr_wr_luma_enb0 <= de_luma_vld & (de_row_flag[0] ==1'b1) ;
dpr_wr_luma_enb1 <= de_luma_vld & (de_row_flag[0] ==1'b1) ;
dpr_wr_luma_enb2 <= (de_luma_vld & (de_row_flag[0] ==1'b0)) || lowest_lu_enb ;
dpr_wr_luma_enb3 <= (de_luma_vld & (de_row_flag[0] ==1'b0)) || lowest_lu_enb ;
if(dpr_wr_luma_enb0 | dpr_wr_luma_enb1 | dpr_wr_luma_enb2 | dpr_wr_luma_enb3 )
begin
dpr_wr_luma0_addr <= dpr_wr_luma0_addr + 1;
dpr_wr_luma1_addr <= dpr_wr_luma1_addr + 1;
end
else
begin
dpr_wr_luma0_addr <= 0;
dpr_wr_luma1_addr <= 0;
end
end
end
end
always @(posedge sys_clk)
begin
if(sys_rstn==1'b0)
begin
dpr_wr_chroma_u_addr <= 0;
dpr_wr_chroma_u_enb0 <= 0;
dpr_wr_chroma_u_enb1 <= 0;
end
else
if ( fill_odd_even == 1'b0)
begin
dpr_wr_chroma_u_enb0 <= mpu_cmd_vld & (pass_chroma_cnt==2'b00) & (state==st_rd_chroma_u);
dpr_wr_chroma_u_enb1 <= mpu_cmd_vld & (pass_chroma_cnt==2'b10) & (state==st_rd_chroma_u);
if(state == st_rd_chroma_u)
begin
if(dpr_wr_chroma_u_enb0 | dpr_wr_chroma_u_enb1)
begin
dpr_wr_chroma_u_addr <= dpr_wr_chroma_u_addr + 1;
end
end
else
begin
dpr_wr_chroma_u_addr <= 0;
end
end
else
begin
dpr_wr_chroma_u_enb0 <= de_u_vld & (de_row_flag[1:0] ==2'b10) ;
dpr_wr_chroma_u_enb1 <= (de_u_vld & (de_row_flag[1:0] ==2'b00)) || lowest_u_enb ;
if(dpr_wr_chroma_u_enb0 | dpr_wr_chroma_u_enb1)
begin
dpr_wr_chroma_u_addr <= dpr_wr_chroma_u_addr + 1;
end
else
begin
dpr_wr_chroma_u_addr <= 0;
end
end
end
always @(posedge sys_clk)
begin
if(sys_rstn==1'b0)
begin
dpr_wr_chroma_v_addr <= 0;
dpr_wr_chroma_v_enb0 <= 0;
dpr_wr_chroma_v_enb1 <= 0;
end
else
if ( fill_odd_even == 1'b0)
begin
dpr_wr_chroma_v_enb0 <= mpu_cmd_vld & (pass_chroma_cnt==2'b00) & (state==st_rd_chroma_v);
dpr_wr_chroma_v_enb1 <= mpu_cmd_vld & (pass_chroma_cnt==2'b10) & (state==st_rd_chroma_v);
if(state == st_rd_chroma_v)
begin
if(dpr_wr_chroma_v_enb0 | dpr_wr_chroma_v_enb1)
begin
dpr_wr_chroma_v_addr <= dpr_wr_chroma_v_addr + 1;
end
end
else
begin
dpr_wr_chroma_v_addr <= 0;
end
end
else
begin
dpr_wr_chroma_v_enb0 <= de_v_vld & (de_row_flag[1:0] ==2'b10) ;
dpr_wr_chroma_v_enb1 <= (de_v_vld & (de_row_flag[1:0] ==2'b00)) || lowest_v_enb;
if(dpr_wr_chroma_v_enb0 | dpr_wr_chroma_v_enb1)
begin
dpr_wr_chroma_v_addr <= dpr_wr_chroma_v_addr + 1;
end
else
begin
dpr_wr_chroma_v_addr <= 0;
end
end
end
dpram16x1k luma_buf0(
.addra(dpr_wr_luma0_addr),
.addrb(dpr_rd_luma0_addr),
.clka(sys_clk),
.clkb(dac_clk),
.dina(dpr_wr_lu0_data[15:0]),
.doutb(luma0),
.wea(dpr_wr_luma_enb0)
);
dpram16x1k luma_buf1(
.addra(dpr_wr_luma1_addr),
.addrb(dpr_rd_luma1_addr),
.clka(sys_clk),
.clkb(dac_clk),
.dina(dpr_wr_lu1_data[15:0]),
.doutb(luma1),
.wea(dpr_wr_luma_enb1)
);
dpram16x1k luma_buf2(
.addra(dpr_wr_luma0_addr),
.addrb(dpr_rd_luma0_addr),
.clka(sys_clk),
.clkb(dac_clk),
.dina(dpr_wr_lu0_data[15:0]),
.doutb(luma2),
.wea(dpr_wr_luma_enb2)
);
dpram16x1k luma_buf3(
.addra(dpr_wr_luma1_addr),
.addrb(dpr_rd_luma1_addr),
.clka(sys_clk),
.clkb(dac_clk),
.dina(dpr_wr_lu1_data[15:0]),
.doutb(luma3),
.wea(dpr_wr_luma_enb3)
);
dpram32x512 chroma_u_buf0(
.addra(dpr_wr_chroma_u_addr),
.addrb(dpr_rd_chroma_u_addr),
.clka(sys_clk),
.clkb(dac_clk),
.dina(dpr_wr_data),
.doutb(chroma_u0),
.wea(dpr_wr_chroma_u_enb0)
);
dpram32x512 chroma_u_buf1(
.addra(dpr_wr_chroma_u_addr),
.addrb(dpr_rd_chroma_u_addr),
.clka(sys_clk),
.clkb(dac_clk),
.dina(dpr_wr_data),
.doutb(chroma_u1),
.wea(dpr_wr_chroma_u_enb1)
);
dpram32x512 chroma_v_buf0(
.addra(dpr_wr_chroma_v_addr),
.addrb(dpr_rd_chroma_v_addr),
.clka(sys_clk),
.clkb(dac_clk),
.dina(dpr_wr_data),
.doutb(chroma_v0),
.wea(dpr_wr_chroma_v_enb0)
);
dpram32x512 chroma_v_buf1(
.addra(dpr_wr_chroma_v_addr),
.addrb(dpr_rd_chroma_v_addr),
.clka(sys_clk),
.clkb(dac_clk),
.dina(dpr_wr_data),
.doutb(chroma_v1),
.wea(dpr_wr_chroma_v_enb1)
);
endmodule?? 快捷鍵說明
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