LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.numeric_std.all;entity TIME is  port(    CLK         : in std_logic;   --4096 Hz    ENABLE_10MS : in    std_logic;    MEASURE     : in    std_logic;    SET_ZERO    : in    std_logic;    M_TIME      : out   std_logic_vector(13 downto 0)  );end entity TIME;architecture BEHAVIORAL_TIME of TIME is  signal REG_OUT : std_logic_vector(13 downto 0);  signal ADD_OUT : std_logic_vector(13 downto 0);  signal ADD     : std_logic_vector(13 downto 0);    begin  ADD <= "00000000000001";  reg : process(CLK)  begin    if CLK'event and CLK='1' then       if SET_ZERO = '1' THEN          REG_OUT <= (others => '0');       elsif ENABLE_10ms = '1' AND MEASURE = '1' THEN          REG_OUT <= ADD_OUT;       end if;     end if;   end process;      ADD_OUT <= std_logic_vector(unsigned(REG_OUT)+unsigned(ADD));      M_TIME <= REG_OUT;end architecture BEHAVIORAL_TIME;