?? stop_watch_reference.vhd
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LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;ENTITY stop_watch_reference IS port( CLK : in std_logic; --4096 Hz RESET : in std_logic; -- LOW active KEY1 : in std_logic; -- LOW active KEY2 : in std_logic; -- LOW active DISPL_1 : out std_logic_vector (6 DOWNTO 0); DISPL_10 : out std_logic_vector (6 DOWNTO 0); DISPL_100 : out std_logic_vector (6 DOWNTO 0); DISPL_1000 : out std_logic_vector (6 DOWNTO 0) );END stop_watch_reference;ARCHITECTURE reference_stop_watch OF stop_watch_reference IS signal STOP_TIME : integer; signal STOP_TIME_L1 : integer; signal STOP_TIME_L2 : integer; signal STOP_TIME_L3 : integer; signal STOP_TIME_L4 : integer; signal CLK_COUNT : integer; type T_STATE is (START, MEASURE_CONT, MEASURE_STOP, MEASURE_INTERM); signal ACTUAL_STATE, NEXT_STATE : T_STATE; function int_2_7seg ( insig : integer) return std_logic_vector is variable pattern : std_logic_vector(6 downto 0); begin -- int_2_7seg case insig is when 0 => pattern := "1111110"; when 1 => pattern := "1100000"; when 2 => pattern := "1011011"; when 3 => pattern := "1110011"; when 4 => pattern := "1100101"; when 5 => pattern := "0110111"; when 6 => pattern := "0111111"; when 7 => pattern := "1100010"; when 8 => pattern := "1111111"; when 9 => pattern := "1110111"; when others => pattern := "0000000"; end case; return pattern; end int_2_7seg;BEGIN ----------------------------------------------------------------------------------- process(CLK) begin if CLK'event and CLK = '1' then STOP_TIME_L1 <= STOP_TIME; STOP_TIME_L2 <= STOP_TIME_L1; STOP_TIME_L3 <= STOP_TIME_L2; STOP_TIME_L4 <= STOP_TIME_L3; end if; end process; ----------------------------------------------------------------------------------- process(STOP_TIME_L4) begin DISPL_1000 <= int_2_7seg( ( STOP_TIME_L4/1000 ) rem 10 ) after 6800 us; DISPL_100 <= int_2_7seg( ( STOP_TIME_L4/100 ) rem 10 ) after 6800 us; DISPL_10 <= int_2_7seg( ( STOP_TIME_L4/10 ) rem 10 ) after 6800 us; DISPL_1 <= int_2_7seg( ( STOP_TIME_L4 ) rem 10 ) after 6800 us; end process; ----------------------------------------------------------------------------------- process (CLK_COUNT,ACTUAL_STATE) begin case ACTUAL_STATE is when MEASURE_INTERM => STOP_TIME <= STOP_TIME; when others => STOP_TIME <= CLK_COUNT*100/4096; end case; end process; ----------------------------------------------------------------------------------- process (CLK,ACTUAL_STATE,RESET) begin if reset='1' then CLK_COUNT <= 0; else case ACTUAL_STATE is when START => CLK_COUNT <= 0; when MEASURE_CONT => if CLK'event and CLK = '1' then CLK_COUNT <= CLK_COUNT +1; end if; when MEASURE_INTERM => if CLK'event and CLK = '1' then CLK_COUNT <= CLK_COUNT +1; end if; when others => end case; end if; end process; ----------------------------------------------------------------------------------- process (KEY1, KEY2,RESET) begin if reset='1' then ACTUAL_STATE <= START; else case ACTUAL_STATE is when START => if KEY1'event and KEY1 = '1' then ACTUAL_STATE <= MEASURE_CONT; end if; when MEASURE_CONT => if KEY1'event and KEY1 = '1' then ACTUAL_STATE <= MEASURE_STOP; elsif KEY2'event and KEY2 = '1' then ACTUAL_STATE <= MEASURE_INTERM; end if; when MEASURE_STOP => if KEY2'event and KEY2 = '1' then ACTUAL_STATE <= START; elsif KEY1'event and KEY1 = '1' then ACTUAL_STATE <= MEASURE_CONT; end if; when MEASURE_INTERM => if KEY1'event and KEY1 = '1' then ACTUAL_STATE <= MEASURE_STOP; elsif KEY2'event and KEY2 = '1' then ACTUAL_STATE <= MEASURE_CONT; end if; when others => end case; end if; end process;END reference_stop_watch;
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