?? config_state_machine.vhd
字號:
-------------------------------------------------------------------------------
-- --
-- Title : config_state machine.vhd --
-- Modified : 04/03/2005 --
-- Author : Altera Component Applications --
-- --
-------------------------------------------------------------------------------
--
-- Description: This design contains the configuration state machine (SM).
--
-- Note:
-- 1. When max_en is '0' the MAX device will NOT attempt to configure the device
-- 2. RESET_n is active low signal to reset flash and FPGA and then configure FPGA.
-- 3. SM will stop at "STATE_CONF_DONE" state if "Enable INIT_DONE Output" is disabled
-- SM will enter "STATE_INIT_DONE" only if "Enable INIT_DONE Output" is enabled
-- 4. Refer to documentation for details on functionality of this design.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
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