<!--
This XML file (created on Sun Oct 21 10:19:16 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>7.1</ver>
<schema>quartus_version_7.1_build_156.xsd</schema>
<license>
	<host_id>000475a7c517</host_id>
	<nic_id>000475a7c517</nic_id>
	<cdrive_id>dcec3435</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>7.1</version>
	<build>Build 156</build>
	<binary_type>32</binary_type>
	<module>quartus_tan</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Sun Oct 21 10:19:17 2007</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1799</cpu_freq>
	</cpu>
	<ram units="MB">768</ram>
</machine>
<project>E:/mywork/new_pwm/new_pwm</project>
<revision>new_pwm</revision>
<compilation_summary>
	<flow_status>Successful - Sun Oct 21 10:19:16 2007</flow_status>
	<quartus_ii_version>7.1 Build 156 04/30/2007 SJ Full Version</quartus_ii_version>
	<revision_name>new_pwm</revision_name>
	<top_level_entity_name>new_pwm</top_level_entity_name>
	<family>Cyclone II</family>
	<met_timing_requirements>Yes</met_timing_requirements>
	<total_logic_elements>43 / 4,608 ( &lt; 1 % )</total_logic_elements>
	<total_combinational_functions>31 / 4,608 ( &lt; 1 % )</total_combinational_functions>
	<dedicated_logic_registers>37 / 4,608 ( &lt; 1 % )</dedicated_logic_registers>
	<total_registers>37</total_registers>
	<total_pins>16 / 89 ( 18 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>0 / 119,808 ( 0 % )</total_memory_bits>
	<embedded_multiplier_9_bit_elements>0 / 26 ( 0 % )</embedded_multiplier_9_bit_elements>
	<total_plls>0 / 2 ( 0 % )</total_plls>
	<device>EP2C5T144C6</device>
	<timing_models>Final</timing_models>
</compilation_summary>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off new_pwm -c new_pwm --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>on</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: th for register &quot;period[5]&quot; (data pin = &quot;wrData[5]&quot;, clock pin = &quot;clk&quot;) is 0.570 ns</info>
	<info>Info: - Shortest pin to register delay is 2.059 ns</info>
	<info>Info: Total interconnect delay = 0.827 ns ( 40.17 % )</info>
	<info>Info: Total cell delay = 1.232 ns ( 59.83 % )</info>
	<info>Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.059 ns; Loc. = LCFF_X24_Y8_N13; Fanout = 1; REG Node = &apos;period[5]&apos;</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>4.999 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>6.383 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>0.570 ns</actual>
	</nonclk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>304.51 MHz ( period = 3.284 ns )</actual>
	</clk>
</performance>
</talkback>