?? new_pwm.fit.talkback.xml
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<!--
This XML file (created on Sun Oct 21 10:19:12 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to license.txt.
-->
<talkback>
<ver>7.1</ver>
<schema>quartus_version_7.1_build_156.xsd</schema>
<license>
<host_id>000475a7c517</host_id>
<nic_id>000475a7c517</nic_id>
<cdrive_id>dcec3435</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>7.1</version>
<build>Build 156</build>
<binary_type>32</binary_type>
<module>quartus_fit</module>
<edition>Full Version</edition>
<eval>Licensed</eval>
<compilation_end_time>Sun Oct 21 10:19:12 2007</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">1799</cpu_freq>
</cpu>
<ram units="MB">768</ram>
</machine>
<project>E:/mywork/new_pwm/new_pwm</project>
<revision>new_pwm</revision>
<compilation_summary>
<flow_status>Successful - Sun Oct 21 10:19:12 2007</flow_status>
<quartus_ii_version>7.1 Build 156 04/30/2007 SJ Full Version</quartus_ii_version>
<revision_name>new_pwm</revision_name>
<top_level_entity_name>new_pwm</top_level_entity_name>
<family>Cyclone II</family>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>43 / 4,608 ( < 1 % )</total_logic_elements>
<total_combinational_functions>31 / 4,608 ( < 1 % )</total_combinational_functions>
<dedicated_logic_registers>37 / 4,608 ( < 1 % )</dedicated_logic_registers>
<total_registers>37</total_registers>
<total_pins>16 / 89 ( 18 % )</total_pins>
<total_virtual_pins>0</total_virtual_pins>
<total_memory_bits>0 / 119,808 ( 0 % )</total_memory_bits>
<embedded_multiplier_9_bit_elements>0 / 26 ( 0 % )</embedded_multiplier_9_bit_elements>
<total_plls>0 / 2 ( 0 % )</total_plls>
<device>EP2C5T144C6</device>
<timing_models>Final</timing_models>
</compilation_summary>
<resource_usage_summary>
<rsc name="Total logic elements" util="1" max=" 4608 " type="int">43 </rsc>
<rsc name="-- Combinational with no register" type="int">6</rsc>
<rsc name="-- Register only" type="int">12</rsc>
<rsc name="-- Combinational with a register" type="int">25</rsc>
<rsc name="Logic element usage by number of LUT inputs" type="text"></rsc>
<rsc name="-- 4 input functions" type="int">3</rsc>
<rsc name="-- 3 input functions" type="int">12</rsc>
<rsc name="-- <=2 input functions" type="int">16</rsc>
<rsc name="-- Register only" type="int">12</rsc>
<rsc name="Logic elements by mode" type="text"></rsc>
<rsc name="-- normal mode" type="int">9</rsc>
<rsc name="-- arithmetic mode" type="int">22</rsc>
<rsc name="Total registers*" util="1" max=" 4851 " type="int">37 </rsc>
<rsc name="-- Dedicated logic registers" util="1" max=" 4608 " type="int">37 </rsc>
<rsc name="-- I/O registers" util="0" max=" 243 " type="int">0 </rsc>
<rsc name="Total LABs: partially or completely used" util="1" max=" 288 " type="int">4 </rsc>
<rsc name="User inserted logic elements" type="int">0</rsc>
<rsc name="Virtual pins" type="int">0</rsc>
<rsc name="I/O pins" util="18" max=" 89 " type="int">16 </rsc>
<rsc name="-- Clock pins" util="75" max=" 4 " type="int">3 </rsc>
<rsc name="Global signals" type="int">1</rsc>
<rsc name="M4Ks" util="0" max=" 26 " type="int">0 </rsc>
<rsc name="Total memory bits" util="0" max=" 119808 " type="int">0 </rsc>
<rsc name="Total RAM block bits" util="0" max=" 119808 " type="int">0 </rsc>
<rsc name="Embedded Multiplier 9-bit elements" util="0" max=" 26 " type="int">0 </rsc>
<rsc name="PLLs" util="0" max=" 2 " type="int">0 </rsc>
<rsc name="Global clocks" util="13" max=" 8 " type="int">1 </rsc>
<rsc name="Maximum fan-out node" type="text">clk~clkctrl</rsc>
<rsc name="Maximum fan-out" type="int">37</rsc>
<rsc name="Highest non-global fan-out signal" type="text">Equal0~111</rsc>
<rsc name="Highest non-global fan-out" type="int">12</rsc>
<rsc name="Total fan-out" type="int">208</rsc>
<rsc name="Average fan-out" type="float">2.21</rsc>
</resource_usage_summary>
<control_signals>
<row>
<name>clk</name>
<location>PIN_17</location>
<fan_out>37</fan_out>
<usage>Clock</usage>
<global>yes</global>
<global_resource_used>Global Clock</global_resource_used>
<global_line_name>GCLK2</global_line_name>
</row>
</control_signals>
<non_global_high_fan_out_signals>
<row>
<name>counter[11]</name>
<fan_out>3</fan_out>
</row>
<row>
<name>counter[10]</name>
<fan_out>3</fan_out>
</row>
<row>
<name>counter[9]</name>
<fan_out>3</fan_out>
</row>
<row>
<name>counter[8]</name>
<fan_out>3</fan_out>
</row>
<row>
<name>counter[7]</name>
<fan_out>3</fan_out>
</row>
<row>
<name>counter[6]</name>
<fan_out>3</fan_out>
</row>
<row>
<name>counter[5]</name>
<fan_out>3</fan_out>
</row>
<row>
<name>counter[4]</name>
<fan_out>3</fan_out>
</row>
<row>
<name>counter[3]</name>
<fan_out>3</fan_out>
</row>
<row>
<name>counter[2]</name>
<fan_out>3</fan_out>
</row>
</non_global_high_fan_out_signals>
<interconnect_usage_summary>
<rsc name="Local interconnects" util="1" max=" 4608 " type="int">25 </rsc>
<rsc name="Block interconnects" util="1" max=" 15666 " type="int">58 </rsc>
<rsc name="R4 interconnects" util="1" max=" 13328 " type="int">34 </rsc>
<rsc name="R24 interconnects" util="0" max=" 652 " type="int">0 </rsc>
<rsc name="C4 interconnects" util="1" max=" 11424 " type="int">20 </rsc>
<rsc name="C16 interconnects" util="1" max=" 812 " type="int">3 </rsc>
<rsc name="Global clocks" util="13" max=" 8 " type="int">1 </rsc>
<rsc name="Direct links" util="1" max=" 15666 " type="int">19 </rsc>
</interconnect_usage_summary>
<mep_data>
<command_line>quartus_fit --read_settings_files=on --write_settings_files=off new_pwm -c new_pwm</command_line>
</mep_data>
<software_data>
<smart_recompile>on</smart_recompile>
</software_data>
<messages>
<warning>Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.</warning>
<warning>Warning: Found 1 output pins without output pin load capacitance assignment</warning>
<warning>Warning: No exact pin location assignment(s) for 16 pins of 16 total pins</warning>
<info>Info: Generated suppressed messages file E:/mywork/new_pwm/new_pwm.fit.smsg</info>
<info>Info: Delay annotation completed successfully</info>
<info>Info: Pin "PwmOut" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis</info>
<info>Info: Started post-fitting delay annotation</info>
<info>Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.</info>
</messages>
<fitter_settings>
<row>
<option>Device</option>
<setting>AUTO</setting>
</row>
<row>
<option>Fit Attempts to Skip</option>
<setting>0</setting>
<default_value>0.0</default_value>
</row>
<row>
<option>Use smart compilation</option>
<setting>On</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Always Enable Input Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Router Timing Optimization Level</option>
<setting>Normal</setting>
<default_value>Normal</default_value>
</row>
<row>
<option>Placement Effort Multiplier</option>
<setting>1.0</setting>
<default_value>1.0</default_value>
</row>
<row>
<option>Router Effort Multiplier</option>
<setting>1.0</setting>
<default_value>1.0</default_value>
</row>
<row>
<option>Optimize Hold Timing</option>
<setting>IO Paths and Minimum TPD Paths</setting>
<default_value>IO Paths and Minimum TPD Paths</default_value>
</row>
<row>
<option>Optimize Fast-Corner Timing</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>PowerPlay Power Optimization</option>
<setting>Normal compilation</setting>
<default_value>Normal compilation</default_value>
</row>
<row>
<option>Optimize Timing</option>
<setting>Normal compilation</setting>
<default_value>Normal compilation</default_value>
</row>
<row>
<option>Optimize IOC Register Placement for Timing</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Limit to One Fitting Attempt</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Final Placement Optimizations</option>
<setting>Automatically</setting>
<default_value>Automatically</default_value>
</row>
<row>
<option>Fitter Aggressive Routability Optimizations</option>
<setting>Automatically</setting>
<default_value>Automatically</default_value>
</row>
<row>
<option>Fitter Initial Placement Seed</option>
<setting>1</setting>
<default_value>1</default_value>
</row>
<row>
<option>PCI I/O</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Weak Pull-Up Resistor</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Enable Bus-Hold Circuitry</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Auto Global Memory Control Signals</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Auto Delay Chains</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Merge PLLs</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore PLL Mode When Merging PLLs</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Perform Physical Synthesis for Combinational Logic for Fitting</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Perform Physical Synthesis for Combinational Logic for Performance</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Perform Register Duplication for Performance</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Perform Logic to Memory Mapping for Fitting</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Perform Register Retiming for Performance</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Perform Asynchronous Signal Pipelining</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Fitter Effort</option>
<setting>Auto Fit</setting>
<default_value>Auto Fit</default_value>
</row>
<row>
<option>Physical Synthesis Effort Level</option>
<setting>Normal</setting>
<default_value>Normal</default_value>
</row>
<row>
<option>Auto Global Clock</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Global Register Control Signals</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Stop After Congestion Map Generation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Save Intermediate Fitting Results</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
</fitter_settings>
<fitter_device_options>
<row>
<option>Enable user-supplied start-up clock (CLKUSR)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable device-wide reset (DEV_CLRn)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable device-wide output enable (DEV_OE)</option>
<setting>Off</setting>
</row>
<row>
<option>Enable INIT_DONE output</option>
<setting>Off</setting>
</row>
<row>
<option>Configuration scheme</option>
<setting>Active Serial</setting>
</row>
<row>
<option>Error detection CRC</option>
<setting>Off</setting>
</row>
<row>
<option>nCEO</option>
<setting>As output driving ground</setting>
</row>
<row>
<option>Reserve all unused pins</option>
<setting>As output driving ground</setting>
</row>
<row>
<option>Base pin-out file on sameframe device</option>
<setting>Off</setting>
</row>
</fitter_device_options>
<input_pins>
<row>
<name>addr</name>
<pin__>100</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>28</x_coordinate>
<y_coordinate>11</y_coordinate>
<cell_number>1</cell_number>
<combinational_fan_out>2</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>3.3-V LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>clk</name>
<pin__>17</pin__>
<i_o_bank>1</i_o_bank>
<x_coordinate>0</x_coordinate>
<y_coordinate>6</y_coordinate>
<cell_number>0</cell_number>
<combinational_fan_out>1</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>yes</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>3.3-V LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>wrData[0]</name>
<pin__>94</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>28</x_coordinate>
<y_coordinate>9</y_coordinate>
<cell_number>2</cell_number>
<combinational_fan_out>2</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>3.3-V LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>wrData[10]</name>
<pin__>92</pin__>
<i_o_bank>3</i_o_bank>
<x_coordinate>28</x_coordinate>
<y_coordinate>8</y_coordinate>
<cell_number>1</cell_number>
<combinational_fan_out>2</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
<pci_i_o_enabled>no</pci_i_o_enabled>
<bus_hold>no</bus_hold>
<weak_pull_up>Off</weak_pull_up>
<i_o_standard>3.3-V LVTTL</i_o_standard>
<termination>Off</termination>
<location_assigned_by>Fitter</location_assigned_by>
</row>
<row>
<name>wrData[11]</name>
<pin__>113</pin__>
<i_o_bank>2</i_o_bank>
<x_coordinate>26</x_coordinate>
<y_coordinate>14</y_coordinate>
<cell_number>1</cell_number>
<combinational_fan_out>2</combinational_fan_out>
<registered_fan_out>0</registered_fan_out>
<global>no</global>
<input_register>no</input_register>
<power_up_high>no</power_up_high>
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