?? new_pwm.map.talkback.xml
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<!--
This XML file (created on Thu Nov 15 10:18:48 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>7.1</ver>
<schema>quartus_version_7.1_build_178.xsd</schema>
<license>
<host_id>000475a7c517</host_id>
<nic_id>000475a7c517</nic_id>
<cdrive_id>dcec3435</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>7.1</version>
<build>Build 178</build>
<service_pack_label>1</service_pack_label>
<binary_type>32</binary_type>
<module>quartus_map</module>
<edition>Web Edition</edition>
<eval>Licensed</eval>
<compilation_end_time>Thu Nov 15 10:18:49 2007</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">1800</cpu_freq>
</cpu>
<ram units="MB">768</ram>
</machine>
<project>E:/mywork/new_pwm/new_pwm</project>
<revision>new_pwm</revision>
<compilation_summary>
<flow_status>Successful - Thu Nov 15 10:18:48 2007</flow_status>
<quartus_ii_version>7.1 Build 178 06/25/2007 SP 1 SJ Web Edition</quartus_ii_version>
<revision_name>new_pwm</revision_name>
<top_level_entity_name>new_pwm</top_level_entity_name>
<family>Cyclone</family>
<met_timing_requirements>N/A</met_timing_requirements>
<total_logic_elements>N/A until Partition Merge</total_logic_elements>
<total_pins>N/A until Partition Merge</total_pins>
<total_virtual_pins>N/A until Partition Merge</total_virtual_pins>
<total_memory_bits>N/A until Partition Merge</total_memory_bits>
<total_plls>N/A until Partition Merge</total_plls>
</compilation_summary>
<eda_tools>
<eda_tool type="eda_design_synthesis">Design Compiler</eda_tool>
<eda_tool type="eda_simulation">ModelSim (VHDL)</eda_tool>
<eda_tool type="eda_timing_analysis">PrimeTime (VHDL)</eda_tool>
</eda_tools>
<mep_data>
<command_line>quartus_map --read_settings_files=on --write_settings_files=off new_pwm -c new_pwm</command_line>
</mep_data>
<software_data>
<smart_recompile>on</smart_recompile>
</software_data>
<messages>
<info>Info: Elaborating entity "new_pwm" for the top level hierarchy</info>
<info>Info: Found 1 design units, including 1 entities, in source file Block1.bdf</info>
<info>Info: Found entity 1: Block1</info>
<info>Info: Found 2 design units, including 1 entities, in source file ../counter_set/counter_set.vhd</info>
<info>Info: Found entity 1: counter_set</info>
</messages>
<analysis___synthesis_settings>
<row>
<option>Top-level entity name</option>
<setting>new_pwm</setting>
<default_value>new_pwm</default_value>
</row>
<row>
<option>Family name</option>
<setting>Cyclone</setting>
<default_value>Stratix II</default_value>
</row>
<row>
<option>Type of Retiming Performed During Resynthesis</option>
<setting>Full</setting>
</row>
<row>
<option>Resynthesis Optimization Effort</option>
<setting>Normal</setting>
</row>
<row>
<option>Physical Synthesis Level for Resynthesis</option>
<setting>Normal</setting>
</row>
<row>
<option>Use Generated Physical Constraints File</option>
<setting>On</setting>
</row>
<row>
<option>Use smart compilation</option>
<setting>On</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Restructure Multiplexers</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Create Debugging Nodes for IP Cores</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Preserve fewer node names</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Disable OpenCore Plus hardware evaluation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Verilog Version</option>
<setting>Verilog_2001</setting>
<default_value>Verilog_2001</default_value>
</row>
<row>
<option>VHDL Version</option>
<setting>VHDL93</setting>
<default_value>VHDL93</default_value>
</row>
<row>
<option>State Machine Processing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Safe State Machine</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Extract Verilog State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Extract VHDL State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore Verilog initial constructs</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Add Pass-Through Logic to Inferred RAMs</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>NOT Gate Push-Back</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Power-Up Don't Care</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Redundant Logic Cells</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Remove Duplicate Registers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore CARRY Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore CASCADE Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore ROW GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore LCELL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore SOFT Buffers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Limit AHDL Integers to 32 Bits</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Optimization Technique -- Cyclone</option>
<setting>Balanced</setting>
<default_value>Balanced</default_value>
</row>
<row>
<option>Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III</option>
<setting>70</setting>
<default_value>70</default_value>
</row>
<row>
<option>Auto Carry Chains</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Open-Drain Pins</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Perform WYSIWYG Primitive Resynthesis</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Perform gate-level register retiming</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow register retiming to trade off Tsu/Tco with Fmax</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto ROM Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto RAM Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Shift Register Replacement</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Auto Clock Enable Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Allow Synchronous Control Signals</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Force Use of Synchronous Clear Signals</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Auto RAM Block Balancing</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto RAM to Logic Cell Conversion</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Auto Resource Sharing</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any RAM Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any ROM Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any Shift Register Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore translate_off and synthesis_off directives</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Show Parameter Settings Tables in Synthesis Report</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore Maximum Fan-Out Assignments</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Retiming Meta-Stability Register Sequence Length</option>
<setting>2</setting>
<default_value>2</default_value>
</row>
<row>
<option>PowerPlay Power Optimization</option>
<setting>Normal compilation</setting>
<default_value>Normal compilation</default_value>
</row>
<row>
<option>HDL message level</option>
<setting>Level2</setting>
<default_value>Level2</default_value>
</row>
<row>
<option>Suppress Register Optimization Related Messages</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Number of Removed Registers Reported in Synthesis Report</option>
<setting>100</setting>
<default_value>100</default_value>
</row>
<row>
<option>Clock MUX Protection</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
</analysis___synthesis_settings>
</talkback>
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