; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[0]    ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[1]    ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[2]    ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[3]    ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[4]    ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[5]    ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[6]    ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[7]    ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[8]    ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[9]    ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[10]   ; clk      ;
; N/A           ; None        ; -4.769 ns ; wr_en      ; duty[11]   ; clk      ;
+---------------+-------------+-----------+------------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sun Oct 21 10:19:15 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off new_pwm -c new_pwm --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 304.51 MHz between source register "counter[0]" and destination register "PwmOut~reg0" (period= 3.284 ns)
    Info: + Longest register to register delay is 3.076 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y8_N9; Fanout = 4; REG Node = 'counter[0]'
        Info: 2: + IC(0.512 ns) + CELL(0.414 ns) = 0.926 ns; Loc. = LCCOMB_X26_Y8_N0; Fanout = 1; COMB Node = 'LessThan0~157'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.997 ns; Loc. = LCCOMB_X26_Y8_N2; Fanout = 1; COMB Node = 'LessThan0~159'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.068 ns; Loc. = LCCOMB_X26_Y8_N4; Fanout = 1; COMB Node = 'LessThan0~161'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.139 ns; Loc. = LCCOMB_X26_Y8_N6; Fanout = 1; COMB Node = 'LessThan0~163'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.210 ns; Loc. = LCCOMB_X26_Y8_N8; Fanout = 1; COMB Node = 'LessThan0~165'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.281 ns; Loc. = LCCOMB_X26_Y8_N10; Fanout = 1; COMB Node = 'LessThan0~167'
        Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.352 ns; Loc. = LCCOMB_X26_Y8_N12; Fanout = 1; COMB Node = 'LessThan0~169'
        Info: 9: + IC(0.000 ns) + CELL(0.159 ns) = 1.511 ns; Loc. = LCCOMB_X26_Y8_N14; Fanout = 1; COMB Node = 'LessThan0~171'
        Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.582 ns; Loc. = LCCOMB_X26_Y8_N16; Fanout = 1; COMB Node = 'LessThan0~173'
        Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.653 ns; Loc. = LCCOMB_X26_Y8_N18; Fanout = 1; COMB Node = 'LessThan0~175'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.724 ns; Loc. = LCCOMB_X26_Y8_N20; Fanout = 1; COMB Node = 'LessThan0~177'
        Info: 13: + IC(0.000 ns) + CELL(0.410 ns) = 2.134 ns; Loc. = LCCOMB_X26_Y8_N22; Fanout = 1; COMB Node = 'LessThan0~178'
        Info: 14: + IC(0.708 ns) + CELL(0.150 ns) = 2.992 ns; Loc. = LCCOMB_X26_Y9_N0; Fanout = 1; COMB Node = 'PwmOut~2'
        Info: 15: + IC(0.000 ns) + CELL(0.084 ns) = 3.076 ns; Loc. = LCFF_X26_Y9_N1; Fanout = 1; REG Node = 'PwmOut~reg0'
        Info: Total cell delay = 1.856 ns ( 60.34 % )
        Info: Total interconnect delay = 1.220 ns ( 39.66 % )
    Info: - Smallest clock skew is 0.006 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.370 ns
            Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 37; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.722 ns) + CELL(0.537 ns) = 2.370 ns; Loc. = LCFF_X26_Y9_N1; Fanout = 1; REG Node = 'PwmOut~reg0'
            Info: Total cell delay = 1.526 ns ( 64.39 % )
            Info: Total interconnect delay = 0.844 ns ( 35.61 % )
        Info: - Longest clock path from clock "clk" to source register is 2.364 ns
            Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 37; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.716 ns) + CELL(0.537 ns) = 2.364 ns; Loc. = LCFF_X25_Y8_N9; Fanout = 4; REG Node = 'counter[0]'
            Info: Total cell delay = 1.526 ns ( 64.55 % )
            Info: Total interconnect delay = 0.838 ns ( 35.45 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "duty[0]" (data pin = "wr_en", clock pin = "clk") is 4.999 ns
    Info: + Longest pin to register delay is 7.399 ns
        Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_96; Fanout = 2; PIN Node = 'wr_en'
        Info: 2: + IC(4.987 ns) + CELL(0.275 ns) = 6.104 ns; Loc. = LCCOMB_X24_Y8_N10; Fanout = 12; COMB Node = 'duty[11]~411'
        Info: 3: + IC(0.635 ns) + CELL(0.660 ns) = 7.399 ns; Loc. = LCFF_X26_Y8_N1; Fanout = 1; REG Node = 'duty[0]'
        Info: Total cell delay = 1.777 ns ( 24.02 % )
        Info: Total interconnect delay = 5.622 ns ( 75.98 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.364 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 37; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.716 ns) + CELL(0.537 ns) = 2.364 ns; Loc. = LCFF_X26_Y8_N1; Fanout = 1; REG Node = 'duty[0]'
        Info: Total cell delay = 1.526 ns ( 64.55 % )
        Info: Total interconnect delay = 0.838 ns ( 35.45 % )
Info: tco from clock "clk" to destination pin "PwmOut" through register "PwmOut~reg0" is 6.383 ns
    Info: + Longest clock path from clock "clk" to source register is 2.370 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 37; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.722 ns) + CELL(0.537 ns) = 2.370 ns; Loc. = LCFF_X26_Y9_N1; Fanout = 1; REG Node = 'PwmOut~reg0'
        Info: Total cell delay = 1.526 ns ( 64.39 % )
        Info: Total interconnect delay = 0.844 ns ( 35.61 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.763 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y9_N1; Fanout = 1; REG Node = 'PwmOut~reg0'
        Info: 2: + IC(0.965 ns) + CELL(2.798 ns) = 3.763 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'PwmOut'
        Info: Total cell delay = 2.798 ns ( 74.36 % )
        Info: Total interconnect delay = 0.965 ns ( 25.64 % )
Info: th for register "period[5]" (data pin = "wrData[5]", clock pin = "clk") is 0.570 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.363 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 37; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.715 ns) + CELL(0.537 ns) = 2.363 ns; Loc. = LCFF_X24_Y8_N13; Fanout = 1; REG Node = 'period[5]'
        Info: Total cell delay = 1.526 ns ( 64.58 % )
        Info: Total interconnect delay = 0.837 ns ( 35.42 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.059 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_89; Fanout = 2; PIN Node = 'wrData[5]'
        Info: 2: + IC(0.827 ns) + CELL(0.149 ns) = 1.975 ns; Loc. = LCCOMB_X24_Y8_N12; Fanout = 1; COMB Node = 'period[5]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.059 ns; Loc. = LCFF_X24_Y8_N13; Fanout = 1; REG Node = 'period[5]'
        Info: Total cell delay = 1.232 ns ( 59.83 % )
        Info: Total interconnect delay = 0.827 ns ( 40.17 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 108 megabytes of memory during processing
    Info: Processing ended: Sun Oct 21 10:19:17 2007
    Info: Elapsed time: 00:00:02