library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity new_pwm is
port(clk:in std_logic;
wrData:in std_logic_vector(15 downto 0);
wr_period:in std_logic_vector(15 downto 0);
PwmOut:out std_logic);
end entity;

architecture one of new_pwm is
shared variable wr_en:std_logic:='0';
shared variable y_en:std_logic;
signal period:std_logic_vector(15 downto 0);
signal duty:std_logic_vector(15 downto 0);
signal counter:std_logic_vector(15 downto 0);
begin
process(clk,wrData)
begin
if rising_edge(clk) then
if(wr_en='0') then
if period=0 then                  ----addr='0' and wr_en='0',write wrData to the period
period<=wr_period;
duty<=duty;
else
period<=period;
duty<=wrData;
end if;
else
period<=period;
duty<=duty;
end if;
end if;
end process;

process(clk)
begin
if falling_edge(clk) then
if counter=0 then 
y_en:='0';
counter<=period;
else 
y_en:='1';
counter<=counter-'1';
end if;
if counter<duty then PwmOut<='0';
elsif counter>=duty and wr_en='1' then PwmOut<='1';
end if;
end if;
wr_en:=y_en;
end process;
end one;