?? new_pwm.vho

?? 一個PWM參數器
?? VHO
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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

-- DATE "10/21/2007 10:19:21"

-- 
-- Device: Altera EP2C5T144C6 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	new_pwm IS
    PORT (
	clk : IN std_logic;
	wr_en : IN std_logic;
	addr : IN std_logic;
	wrData : IN std_logic_vector(11 DOWNTO 0);
	PwmOut : OUT std_logic
	);
END new_pwm;

ARCHITECTURE structure OF new_pwm IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_wr_en : std_logic;
SIGNAL ww_addr : std_logic;
SIGNAL ww_wrData : std_logic_vector(11 DOWNTO 0);
SIGNAL ww_PwmOut : std_logic;
SIGNAL \clk~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[1]~134_combout\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \clk~clkctrl_outclk\ : std_logic;
SIGNAL \wr_en~combout\ : std_logic;
SIGNAL \addr~combout\ : std_logic;
SIGNAL \duty[11]~411_combout\ : std_logic;
SIGNAL \counter[0]~133_combout\ : std_logic;
SIGNAL \period[0]~feeder_combout\ : std_logic;
SIGNAL \period[11]~404_combout\ : std_logic;
SIGNAL \counter[8]~141_combout\ : std_logic;
SIGNAL \period[8]~feeder_combout\ : std_logic;
SIGNAL \counter[10]~154\ : std_logic;
SIGNAL \counter[11]~132_combout\ : std_logic;
SIGNAL \Equal0~108_combout\ : std_logic;
SIGNAL \counter[2]~135_combout\ : std_logic;
SIGNAL \Equal0~110_combout\ : std_logic;
SIGNAL \counter[6]~139_combout\ : std_logic;
SIGNAL \period[6]~feeder_combout\ : std_logic;
SIGNAL \Equal0~109_combout\ : std_logic;
SIGNAL \Equal0~111_combout\ : std_logic;
SIGNAL \counter[0]~144\ : std_logic;
SIGNAL \counter[1]~145\ : std_logic;
SIGNAL \counter[2]~146\ : std_logic;
SIGNAL \counter[3]~136_combout\ : std_logic;
SIGNAL \counter[3]~147\ : std_logic;
SIGNAL \counter[4]~148\ : std_logic;
SIGNAL \counter[5]~138_combout\ : std_logic;
SIGNAL \period[5]~feeder_combout\ : std_logic;
SIGNAL \counter[5]~149\ : std_logic;
SIGNAL \counter[6]~150\ : std_logic;
SIGNAL \counter[7]~140_combout\ : std_logic;
SIGNAL \period[7]~feeder_combout\ : std_logic;
SIGNAL \counter[7]~151\ : std_logic;
SIGNAL \counter[8]~152\ : std_logic;
SIGNAL \counter[9]~142_combout\ : std_logic;
SIGNAL \period[9]~feeder_combout\ : std_logic;
SIGNAL \counter[9]~153\ : std_logic;
SIGNAL \counter[10]~143_combout\ : std_logic;
SIGNAL \counter[4]~137_combout\ : std_logic;
SIGNAL \LessThan0~157_cout\ : std_logic;
SIGNAL \LessThan0~159_cout\ : std_logic;
SIGNAL \LessThan0~161_cout\ : std_logic;
SIGNAL \LessThan0~163_cout\ : std_logic;
SIGNAL \LessThan0~165_cout\ : std_logic;
SIGNAL \LessThan0~167_cout\ : std_logic;
SIGNAL \LessThan0~169_cout\ : std_logic;
SIGNAL \LessThan0~171_cout\ : std_logic;
SIGNAL \LessThan0~173_cout\ : std_logic;
SIGNAL \LessThan0~175_cout\ : std_logic;
SIGNAL \LessThan0~177_cout\ : std_logic;
SIGNAL \LessThan0~178_combout\ : std_logic;
SIGNAL \PwmOut~2_combout\ : std_logic;
SIGNAL \PwmOut~reg0_regout\ : std_logic;
SIGNAL counter : std_logic_vector(11 DOWNTO 0);
SIGNAL duty : std_logic_vector(11 DOWNTO 0);
SIGNAL period : std_logic_vector(11 DOWNTO 0);
SIGNAL \wrData~combout\ : std_logic_vector(11 DOWNTO 0);

BEGIN

ww_clk <= clk;
ww_wr_en <= wr_en;
ww_addr <= addr;
ww_wrData <= wrData;
PwmOut <= ww_PwmOut;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\clk~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \clk~combout\);

\counter[1]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \counter[1]~134_combout\,
	sdata => period(1),
	sload => \Equal0~111_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => counter(1));

\counter[1]~134\ : cycloneii_lcell_comb
-- Equation(s):
-- \counter[1]~134_combout\ = counter(1) & \counter[0]~144\ & VCC # !counter(1) & !\counter[0]~144\
-- \counter[1]~145\ = CARRY(!counter(1) & !\counter[0]~144\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100000101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => counter(1),
	datad => VCC,
	cin => \counter[0]~144\,
	combout => \counter[1]~134_combout\,
	cout => \counter[1]~145\);

\duty[10]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	sdata => \wrData~combout\(10),
	sload => VCC,
	ena => \duty[11]~411_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => duty(10));

\duty[8]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	sdata => \wrData~combout\(8),
	sload => VCC,
	ena => \duty[11]~411_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => duty(8));

\duty[7]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	sdata => \wrData~combout\(7),
	sload => VCC,
	ena => \duty[11]~411_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => duty(7));

\duty[5]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	sdata => \wrData~combout\(5),
	sload => VCC,
	ena => \duty[11]~411_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => duty(5));

\duty[4]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	sdata => \wrData~combout\(4),
	sload => VCC,
	ena => \duty[11]~411_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => duty(4));

\period[1]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	sdata => \wrData~combout\(1),
	sload => VCC,
	ena => \period[11]~404_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => period(1));

\clk~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\clk~clkctrl\ : cycloneii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "falling edge")
-- pragma translate_on
PORT MAP (
	inclk => \clk~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~clkctrl_outclk\);

\wrData[11]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_wrData(11),
	combout => \wrData~combout\(11));

\wr_en~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_wr_en,
	combout => \wr_en~combout\);

\addr~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_addr,
	combout => \addr~combout\);

\duty[11]~411\ : cycloneii_lcell_comb
-- Equation(s):
-- \duty[11]~411_combout\ = !\wr_en~combout\ & \addr~combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \wr_en~combout\,
	datad => \addr~combout\,
	combout => \duty[11]~411_combout\);

\duty[11]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	sdata => \wrData~combout\(11),
	sload => VCC,
	ena => \duty[11]~411_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => duty(11));

\counter[0]~133\ : cycloneii_lcell_comb
-- Equation(s):
-- \counter[0]~133_combout\ = counter(0) $ VCC
-- \counter[0]~144\ = CARRY(counter(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => counter(0),
	datad => VCC,
	combout => \counter[0]~133_combout\,
	cout => \counter[0]~144\);

\wrData[0]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_wrData(0),
	combout => \wrData~combout\(0));

\period[0]~feeder\ : cycloneii_lcell_comb
-- Equation(s):
-- \period[0]~feeder_combout\ = \wrData~combout\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \wrData~combout\(0),
	combout => \period[0]~feeder_combout\);

\period[11]~404\ : cycloneii_lcell_comb
-- Equation(s):
-- \period[11]~404_combout\ = !\wr_en~combout\ & !\addr~combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \wr_en~combout\,
	datad => \addr~combout\,
	combout => \period[11]~404_combout\);

\period[0]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \period[0]~feeder_combout\,
	ena => \period[11]~404_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => period(0));

\counter[8]~141\ : cycloneii_lcell_comb
-- Equation(s):
-- \counter[8]~141_combout\ = counter(8) & (GND # !\counter[7]~151\) # !counter(8) & (\counter[7]~151\ $ GND)
-- \counter[8]~152\ = CARRY(counter(8) # !\counter[7]~151\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101010101111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => counter(8),
	datad => VCC,
	cin => \counter[7]~151\,
	combout => \counter[8]~141_combout\,
	cout => \counter[8]~152\);

\wrData[8]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_wrData(8),
	combout => \wrData~combout\(8));

\period[8]~feeder\ : cycloneii_lcell_comb
-- Equation(s):
-- \period[8]~feeder_combout\ = \wrData~combout\(8)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \wrData~combout\(8),
	combout => \period[8]~feeder_combout\);

\period[8]\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl_outclk\,
	datain => \period[8]~feeder_combout\,
	ena => \period[11]~404_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => period(8));

\counter[8]\ : cycloneii_lcell_ff
12 3 下一頁
?? 文件大小 227 K
?? 上傳用戶 qq569854
?? 所屬分類 VHDL/FPGA/Verilog
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