library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity shift is
port(cp,en,D,CT,c,k,x:in std_logic;
q3,q2,q1,q0:out std_logic);
end shift;
architecture HL of shift is
signal temp:std_logic_vector(3 downto 0);
begin
q3<=temp(3);q2<=temp(2);q1<=temp(1);q0<=temp(0);
process  (cp,en,D,CT,k,x)
begin 
if(c='0') then temp<=(others=>'0');
elsif (CT='1') then temp<=(others=>'1');
elsif(cp' event and cp='1') then

if (en='1') then
if(x='0') then
if (k='0') then
temp(0)<=D;temp(1)<=temp(0);temp(2)<=temp(1);temp(3)<=temp(2);
else
temp(0)<=temp(1);temp(1)<=temp(2);temp(2)<=temp(3);temp(3)<=D;
end if;
elsif(x='1')then
temp(0)<=temp(1);temp(1)<=temp(2);temp(2)<=temp(3);temp(3)<=temp(0);
end if;
end if;
end if;
end process;
end hl;