?? finish.twr
字號(hào):
--------------------------------------------------------------------------------
Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
C:/Xilinx/bin/nt/trce.exe -ise z:\work\speedmes\speedmes.ise -intstyle ise -e 3
-l 3 -s 4 -xml Finish Finish.ncd -o Finish.twr Finish.pcf
Design file: finish.ncd
Physical constraint file: finish.pcf
Device,speed: xc3s200,-4 (PRODUCTION 1.35 2005-01-22)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
AD<0> | 4.090(R)| -1.804(R)|clk_BUFGP | 0.000|
AD<1> | 5.105(R)| -2.615(R)|clk_BUFGP | 0.000|
AD<2> | 4.023(R)| -1.750(R)|clk_BUFGP | 0.000|
AD<3> | 4.381(R)| -2.035(R)|clk_BUFGP | 0.000|
AD<4> | 6.504(R)| -3.737(R)|clk_BUFGP | 0.000|
AD<5> | 3.781(R)| -1.557(R)|clk_BUFGP | 0.000|
AD<6> | 5.697(R)| -3.088(R)|clk_BUFGP | 0.000|
AD<7> | 4.156(R)| -1.856(R)|clk_BUFGP | 0.000|
BTN_A | 5.353(R)| -0.263(R)|clk_BUFGP | 0.000|
reset | 52.162(R)| 0.502(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock sensor1
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
reset | 8.822(R)| -3.483(R)|sensor1_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock sensor2
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
reset | 4.900(R)| -1.646(R)|sensor2_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock sensor3
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
reset | 8.024(R)| -2.819(R)|sensor3_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock sensor4
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
reset | 7.406(R)| -1.827(R)|sensor4_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
AD<0> | 12.787(R)|clk_BUFGP | 0.000|
AD<1> | 14.225(R)|clk_BUFGP | 0.000|
AD<2> | 12.788(R)|clk_BUFGP | 0.000|
AD<3> | 13.170(R)|clk_BUFGP | 0.000|
AD<4> | 12.787(R)|clk_BUFGP | 0.000|
AD<5> | 13.129(R)|clk_BUFGP | 0.000|
AD<6> | 13.500(R)|clk_BUFGP | 0.000|
AD<7> | 13.149(R)|clk_BUFGP | 0.000|
ALE | 11.136(R)|clk_BUFGP | 0.000|
CS | 11.602(R)|clk_BUFGP | 0.000|
LED_A1 | 11.181(R)|clk_BUFGP | 0.000|
RD | 10.213(R)|clk_BUFGP | 0.000|
STATUS<0> | 10.151(R)|clk_BUFGP | 0.000|
STATUS<1> | 10.857(R)|clk_BUFGP | 0.000|
STATUS<2> | 10.544(R)|clk_BUFGP | 0.000|
STATUS<3> | 11.229(R)|clk_BUFGP | 0.000|
STATUS<4> | 10.916(R)|clk_BUFGP | 0.000|
STATUS<5> | 10.231(R)|clk_BUFGP | 0.000|
STATUS<6> | 9.929(R)|clk_BUFGP | 0.000|
STATUS<7> | 9.749(R)|clk_BUFGP | 0.000|
WR | 11.646(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 54.014| | | |
sensor1 | 57.627| | | |
sensor2 | 54.010| | | |
sensor3 | 63.121| | | |
sensor4 | 57.779| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock sensor1
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 8.674| | | |
sensor1 | 6.255| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock sensor2
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 4.200| | | |
sensor2 | 6.641| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock sensor3
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 8.269| | | |
sensor3 | 6.120| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock sensor4
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 7.663| | | |
sensor4 | 6.131| | | |
---------------+---------+---------+---------+---------+
Analysis completed Tue Dec 06 19:07:45 2005
--------------------------------------------------------------------------------
Peak Memory Usage: 111 MB
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