Release 7.1i Map H.38Xilinx Mapping Report File for Design 'Finish'Design Information------------------Command Line   : C:\Xilinx\bin\nt\org-map.exe -ise z:\work\speedmes\speedmes.ise
-intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -o Finish_map.ncd
Finish.ngd Finish.pcf Target Device  : xc3s200Target Package : ft256Target Speed   : -4Mapper Version : spartan3 -- $Revision: 1.26.6.3 $Mapped Date    : Tue Dec 06 19:06:50 2005Design Summary--------------Number of errors:      0Number of warnings:    2Logic Utilization:  Number of Slice Flip Flops:         379 out of   3,840    9%  Number of 4 input LUTs:           3,195 out of   3,840   83%Logic Distribution:  Number of occupied Slices:                        1,753 out of   1,920   91%    Number of Slices containing only related logic:   1,753 out of   1,753  100%    Number of Slices containing unrelated logic:          0 out of   1,753    0%      *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:          3,395 out of   3,840   88%  Number used as logic:              3,195  Number used as a route-thru:         200  Number of bonded IOBs:               28 out of     173   16%  Number of MULT18X18s:                8 out of      12   66%  Number of GCLKs:                     5 out of       8   62%Total equivalent gate count for design:  66,006Additional JTAG gate count for IOBs:  1,344Peak Memory Usage:  136 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:243 - Logical network XLXI_2/_n0008<31> has no load.WARNING:LIT:374 - The above warning message base_net_load_rule is repeated 127
   more times for the following (max. 5 shown):   XLXI_2/_n0008<30>,   XLXI_2/_n0008<29>,   XLXI_2/_n0008<28>,   XLXI_2/_n0008<27>,   XLXI_2/_n0008<26>   To see the details of these warning messages, please use the -detail switch.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP),   BUFGP symbol "sensor1_BUFGP" (output signal=sensor1_BUFGP),   BUFGP symbol "sensor2_BUFGP" (output signal=sensor2_BUFGP),   BUFGP symbol "sensor3_BUFGP" (output signal=sensor3_BUFGP),   BUFGP symbol "sensor4_BUFGP" (output signal=sensor4_BUFGP)INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.Section 4 - Removed Logic Summary---------------------------------   8 block(s) removed  22 block(s) optimized away   8 signal(s) removedSection 5 - Removed Logic-------------------------The trimmed logic reported below is either:   1. part of a cycle   2. part of disabled logic   3. a side-effect of other trimmed logicThe signal "XLXI_4/sensorcount_0_rt4" is unused and has been removed. Unused block "XLXI_4/sensorcount_0_rt4" (ROM) removed.The signal "XLXI_3/sensorcount_0_rt3" is unused and has been removed. Unused block "XLXI_3/sensorcount_0_rt3" (ROM) removed.The signal "XLXI_3/sensorcount_0_rt4" is unused and has been removed. Unused block "XLXI_3/sensorcount_0_rt4" (ROM) removed.The signal "XLXI_2/sensorcount_0_rt3" is unused and has been removed. Unused block "XLXI_2/sensorcount_0_rt3" (ROM) removed.The signal "XLXI_5/sensorcount_0_rt4" is unused and has been removed. Unused block "XLXI_5/sensorcount_0_rt4" (ROM) removed.The signal "XLXI_4/sensorcount_0_rt3" is unused and has been removed. Unused block "XLXI_4/sensorcount_0_rt3" (ROM) removed.The signal "XLXI_5/sensorcount_0_rt3" is unused and has been removed. Unused block "XLXI_5/sensorcount_0_rt3" (ROM) removed.The signal "XLXI_2/sensorcount_0_rt4" is unused and has been removed. Unused block "XLXI_2/sensorcount_0_rt4" (ROM) removed.Optimized Block(s):TYPE 		BLOCKLUT1 		N0_rtLUT1 		N0_rt1LUT1 		N0_rt2LUT1 		N0_rt3LUT1 		N0_rt4LUT1 		N0_rt5LUT1 		N0_rt6LUT1 		N0_rt7LUT2 		XLXI_2/speed__n0046<0>lutLUT2 		XLXI_3/speed__n0046<0>lutLUT2 		XLXI_4/speed__n0046<0>lutLUT2 		XLXI_5/speed__n0046<0>lutGND 		XST_GNDVCC 		XST_VCCMUXCY 		XLXI_2/speed__n0022<0>cyMUXCY 		XLXI_2/speed__n0024<0>cyMUXCY 		XLXI_3/speed__n0022<0>cyMUXCY 		XLXI_3/speed__n0024<0>cyMUXCY 		XLXI_4/speed__n0022<0>cyMUXCY 		XLXI_4/speed__n0024<0>cyMUXCY 		XLXI_5/speed__n0022<0>cyMUXCY 		XLXI_5/speed__n0024<0>cyTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| AD<0>                              | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW |          |          |       || AD<1>                              | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW |          |          |       || AD<2>                              | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW |          |          |       || AD<3>                              | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW |          |          |       || AD<4>                              | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW |          |          |       || AD<5>                              | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW |          |          |       || AD<6>                              | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW |          |          |       || AD<7>                              | IOB     | BIDIR     | LVCMOS25    | 12       | SLOW |          |          |       || ALE                                | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || BTN_A                              | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || CS                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || LED_A1                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || RD                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || STATUS<0>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || STATUS<1>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || STATUS<2>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || STATUS<3>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || STATUS<4>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || STATUS<5>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || STATUS<6>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || STATUS<7>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || WR                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || clk                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || reset                              | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || sensor1                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || sensor2                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || sensor3                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || sensor4                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 28Number of Equivalent Gates for Design = 66,006Number of RPM Macros = 0Number of Hard Macros = 0DCIRESETs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DCMs = 0GCLKs = 5ICAPs = 018X18 Multipliers = 8Block RAMs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 250IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 28XORs = 1829CARRY_INITs = 1099CARRY_SKIPs = 4CARRY_MUXes = 2065Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MUXFs = 25MULT_ANDs = 44 input LUTs used as Route-Thrus = 2004 input LUTs = 3195Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 250Slice Flip Flops = 379SliceMs = 0SliceLs = 1753Slices = 1753F6 Muxes = 0F5 Muxes = 25F8 Muxes = 0F7 Muxes = 0Number of LUT signals with 4 loads = 28Number of LUT signals with 3 loads = 27Number of LUT signals with 2 loads = 1687Number of LUT signals with 1 load = 1353NGM Average fanout of LUT = 2.04NGM Maximum fanout of LUT = 39NGM Average fanin for LUT = 2.4764Number of LUT symbols = 3195