--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1i
--  \   \         Application : sch2vhdl
--  /   /         Filename : Finish.vhf
-- /___/   /\     Timestamp : 12/06/2005 19:04:24
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family spartan3 -flat -suppress -w Finish.sch Finish.vhf
--Design Name: Finish
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity Finish is
   port ( BTN_A   : in    std_logic; 
          clk     : in    std_logic; 
          reset   : in    std_logic; 
          sensor1 : in    std_logic; 
          sensor2 : in    std_logic; 
          sensor3 : in    std_logic; 
          sensor4 : in    std_logic; 
          ALE     : out   std_logic; 
          CS      : out   std_logic; 
          LED_A1  : out   std_logic; 
          RD      : out   std_logic; 
          WR      : out   std_logic; 
          AD      : inout std_logic_vector (7 downto 0); 
          STATUS  : inout std_logic_vector (7 downto 0));
end Finish;

architecture BEHAVIORAL of Finish is
   signal XLXN_38 : std_logic_vector (8 downto 0);
   signal XLXN_39 : std_logic_vector (8 downto 0);
   signal XLXN_40 : std_logic_vector (8 downto 0);
   signal XLXN_41 : std_logic_vector (8 downto 0);
   signal XLXN_53 : std_logic;
   signal XLXN_54 : std_logic;
   signal XLXN_55 : std_logic;
   signal XLXN_56 : std_logic;
   signal XLXN_57 : std_logic;
   signal XLXN_58 : std_logic;
   signal XLXN_59 : std_logic;
   signal XLXN_60 : std_logic;
   component cancommunication
      port ( clk     : in    std_logic; 
             reset   : in    std_logic; 
             sensor1 : in    std_logic_vector (8 downto 0); 
             sensor2 : in    std_logic_vector (8 downto 0); 
             sensor3 : in    std_logic_vector (8 downto 0); 
             sensor4 : in    std_logic_vector (8 downto 0); 
             AD      : inout std_logic_vector (7 downto 0); 
             STATUS  : inout std_logic_vector (7 downto 0); 
             ALE     : out   std_logic; 
             RD      : out   std_logic; 
             WR      : out   std_logic; 
             CS      : out   std_logic; 
             LED_A1  : out   std_logic; 
             s1clk   : in    std_logic; 
             s2clk   : in    std_logic; 
             s3clk   : in    std_logic; 
             s4clk   : in    std_logic; 
             s1clk16 : in    std_logic; 
             s2clk16 : in    std_logic; 
             s3clk16 : in    std_logic; 
             s4clk16 : in    std_logic; 
             BTN_A   : in    std_logic);
   end component;
   
   component speed
      port ( clk       : in    std_logic; 
             sensorclk : in    std_logic; 
             reset     : in    std_logic; 
             s         : out   std_logic_vector (8 downto 0));
   end component;
   
   component signalflash
      port ( clk     : in    std_logic; 
             flash   : inout std_logic; 
             flash16 : inout std_logic);
   end component;
   
begin
   XLXI_1 : cancommunication
      port map (BTN_A=>BTN_A,
                clk=>clk,
                reset=>reset,
                sensor1(8 downto 0)=>XLXN_38(8 downto 0),
                sensor2(8 downto 0)=>XLXN_39(8 downto 0),
                sensor3(8 downto 0)=>XLXN_40(8 downto 0),
                sensor4(8 downto 0)=>XLXN_41(8 downto 0),
                s1clk=>XLXN_53,
                s1clk16=>XLXN_57,
                s2clk=>XLXN_54,
                s2clk16=>XLXN_58,
                s3clk=>XLXN_55,
                s3clk16=>XLXN_59,
                s4clk=>XLXN_56,
                s4clk16=>XLXN_60,
                ALE=>ALE,
                CS=>CS,
                LED_A1=>LED_A1,
                RD=>RD,
                WR=>WR,
                AD(7 downto 0)=>AD(7 downto 0),
                STATUS(7 downto 0)=>STATUS(7 downto 0));
   
   XLXI_2 : speed
      port map (clk=>clk,
                reset=>reset,
                sensorclk=>sensor1,
                s(8 downto 0)=>XLXN_38(8 downto 0));
   
   XLXI_3 : speed
      port map (clk=>clk,
                reset=>reset,
                sensorclk=>sensor2,
                s(8 downto 0)=>XLXN_39(8 downto 0));
   
   XLXI_4 : speed
      port map (clk=>clk,
                reset=>reset,
                sensorclk=>sensor3,
                s(8 downto 0)=>XLXN_40(8 downto 0));
   
   XLXI_5 : speed
      port map (clk=>clk,
                reset=>reset,
                sensorclk=>sensor4,
                s(8 downto 0)=>XLXN_41(8 downto 0));
   
   XLXI_12 : signalflash
      port map (clk=>sensor1,
                flash=>XLXN_53,
                flash16=>XLXN_54);
   
   XLXI_13 : signalflash
      port map (clk=>sensor2,
                flash=>XLXN_55,
                flash16=>XLXN_56);
   
   XLXI_14 : signalflash
      port map (clk=>sensor3,
                flash=>XLXN_57,
                flash16=>XLXN_58);
   
   XLXI_15 : signalflash
      port map (clk=>sensor4,
                flash=>XLXN_59,
                flash16=>XLXN_60);
   
end BEHAVIORAL;