;File kei842.dat

;SFR definitions for ADuC842 Assebler files.

;ADuC842   Apps, Analog Devices Inc.

$NOMOD51

DPP      DATA  084H  ;DATA POINTER - PAGE BYTE

T3FD     DATA  09DH  ;Serial baudrate fraction

T3CON    DATA  09EH  ;Seral baudrate tap

TIMECON  DATA  0A1H  ;TIME COUNTER CONTROL REGISTER

HTHSEC   DATA  0A2H  ;1/128 OF A SECOND COUNTER

SEC      DATA  0A3H  ;SECONDS COUNTER

MIN      DATA  0A4H  ;MINUTES COUNTER

HOUR     DATA  0A5H  ;HOURS COUNTER

INTVAL   DATA  0A6H  ;TIMER INTERVAL

DPCON    DATA  0A7H  ;Data Pointer control

IEIP2    DATA  0A9H  ;INTERRUPT ENABLE 2

PWMCON   DATA  0AEH  ;PWM control

CFG842   DATA  0AFH  ;Configure ADuC842.

PWM0L    DATA  0B1H  ;PWM width low

PWM0H    DATA  0B2H  ;PWM width high

PWM1L    DATA  0B3H  ;PWM cycle low

PWM1H    DATA  0B4H  ;PWM cycle high

SPH      DATA  0B7H  ;Stack pointer high

ECON     DATA  0B9H  ;FLASH CONTROL

EDATA1   DATA  0BCH  ;FLASH DATA1 

EDATA2   DATA  0BDH  ;FLASH DATA2 

EDATA3   DATA  0BEH  ;FLASH DATA3 

EDATA4   DATA  0BFH  ;FLASH DATA4 

WDCON    DATA  0C0H  ;WATCHDOG TIMER CONTROL

CHIPID   DATA  0C2H  ;CHIP ID REGISTER

EADRL    DATA  0C6H  ;EEPROM ADDRESS LOW

EADRH    DATA  0C7H  ;EEPROM ADDRESS HIGH

T2CON    DATA  0C8H  ;Timer 2 control.

RCAP2L   DATA  0caH  ;Reload/capture low byte.

RCAP2H   DATA  0cbH  ;Reload/capture high byte.

TL2      DATA  0CcH  ;Timer 2 low byte.

TH2      DATA  0CdH  ;Timer 2 high byte.

DMAL     DATA  0D2H  ;DMA low,

DMAH     DATA  0D3H  ; high

DMAP     DATA  0D4H  ; and page.

PLLCON   DATA  0D7H  ;CRYSTAL PLL CONTROL REGISTER

ADCCON2  DATA  0D8H  ;ADC control 2

ADCDATAL DATA  0D9H  ;ADC DATA REGISTER

ADCDATAH DATA  0DAH  ;ADC DATA REGISTER

PSMCON   DATA  0DFH  ;POWER SUPPLY MONITOR

ADCCON1  DATA  0efH  ;ADC control 1

ADCOFSL  DATA  0f1H  ;ADC offset low

ADCOFSH  DATA  0f2H  ; and high.

ADCGAINL DATA  0f3H  ;ADC gain low

ADCGAINH DATA  0f4H  ; and high.

ADCCON3  DATA  0f5H  ;ADC control 3.

SPIDAT   DATA  0F7H  ;SPI DATA REGISTER

SPICON   DATA  0F8H  ;SPI CONTROL REGISTER

DAC0L    DATA  0f9H  ;DAC0 LOW BYTE

DAC0H    DATA  0faH  ;DAC0 HIGH BYTE

DAC1L    DATA  0fbH  ;DAC1 LOW BYTE

DAC1H    DATA  0fcH  ;DAC1 HIGH BYTE

DACCON   DATA  0FDH  ;DAC CONTROL REGISTER

;

;Bits.

;

EADC     BIT   0AEH  ;IE.6 - ENABLE ADC INTURRUPT

PSI      BIT   0BFH  ;IP.7 - SPI OR 2-WIRE SERIAL INTERFACE PRIORITY

WDWR     BIT   0C0H  ;WDCON.0 - WATCHDOG WRITE ENABLE BIT

WDE      BIT   0C1H  ;WDCON.1 - WATCHDOG ENABLE

WDS      BIT   0C2H  ;WDCON.2 - WATCHDOG STATUS

WDIR     BIT   0C3H  ;WDCON.3 - WATCHDOG INTERRUPT RESPONSE BIT

PRE0     BIT   0C5H  ;WDCON.4 - WATCHDOG TIMEOUT SELECTION BIT0

PRE1     BIT   0C6H  ;WDCON.5 - WATCHDOG TIMEOUT SELECTION BIT1

PRE2     BIT   0C7H  ;WDCON.6 - WATCHDOG TIMEOUT SELECTION BIT2

PRE3     BIT   0C8H  ;WDCON.7 - WATCHDOG TIMEOUT SELECTION BIT3

SPR0     BIT   0F8H  ;SPICON.0 - SPI BITRATE SELECT BIT0

SPR1     BIT   0F9H  ;SPICON.1 - SPI BITRATE SELECT BIT1

CPHA     BIT   0FAH  ;SPICON.2 - SPI CLOCK PHASE SELECT

CPOL     BIT   0FBH  ;SPICON.3 - SPI CLOCK POLARITY SELECT

SPIM     BIT   0FCH  ;SPICON.4 - SPI MASTER/SLAVE MODE SELECT

SPE      BIT   0FDH  ;SPICON.5 - SPI INTERFACE ENABLE

WCOL     BIT   0FEH  ;SPICON.6 - SPI WRITE COLLISION ERROR FLAG

ISPI     BIT   0FFH  ;SPICON.7 - SPI INTERRUPT BIT



;kei842.dat end================================================kei842.dat end

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