module fosc1 (clkx,clk,lddat,ldsel);
input clk,clkx;
output [7:0] lddat;
output [3:0] ldsel;

reg [22:0] count;
reg [15:0] min;
reg [7:0] lddat_reg;
reg [3:0] ldsel_reg,ledbuf;
reg sec;

always @ (negedge clk)
	begin
	count=count+1;
	if(count==23'h54601e)
		begin
			count=23'h000000;
			sec=~sec;
		end
	end

always @ (count[11:10])
	begin
		case(count[11:10])
			2'b00:ledbuf=min[3:0];
			2'b01:ledbuf=min[7:4];
			2'b10:ledbuf=min[11:8];
			2'b11:ledbuf=min[15:12];
		endcase
	end

always	@ (ledbuf)
	begin
		case(ledbuf)
			4'h0: lddat_reg = 8'hc0;
			4'h1: lddat_reg = 8'hf9;				//顯示1
			4'h2: lddat_reg = 8'ha4;				//顯示2
			4'h3: lddat_reg = 8'hb0;				//顯示3
			4'h4: lddat_reg = 8'h99;				//顯示4
			4'h5: lddat_reg = 8'h92;				//顯示5
			4'h6: lddat_reg = 8'h82;				//顯示6
			4'h7: lddat_reg = 8'hf8;				//顯示7
			4'h8: lddat_reg = 8'h80;				//顯示8
			4'h9: lddat_reg = 8'h90;				//顯示9      
			4'ha: lddat_reg = 8'h88;				//顯示a   
			4'hb: lddat_reg = 8'h83;				//顯示b
			4'hc: lddat_reg = 8'hc6;				//顯示c
			4'hd: lddat_reg = 8'ha1;				//顯示d
			4'he: lddat_reg = 8'h86;				//顯示e
			4'hf: lddat_reg = 8'h8e;				//顯示f
		endcase
	end

always @ (count[11:10])
	begin
		case(count[11:10])
			2'b00:ldsel_reg=4'b0111;
			2'b01:ldsel_reg=4'b1011;
			2'b10:ldsel_reg=4'b1101;
			2'b11:ldsel_reg=4'b1110;
		endcase
	end

always @ (negedge clkx)
	begin	
			min=min+1;
			if(min[3:0]==4'ha)
				begin
					min[3:0]=4'h0;
					min[7:4]=min[7:4]+1;
					if(min[7:4]==4'h6)
						begin
							min[7:4]=4'h0;
							min[11:8]=min[11:8]+1;
							if(min[11:8]==4'ha)
								begin
									min[11:8]=4'h0;
									min[15:12]=min[15:12]+1;
									if(min[15:12]==4'h6) min[15:12]=4'h0;
								end
						end
				end
			
	end

assign lddat=lddat_reg;
assign ldsel=ldsel_reg;	 

endmodule