Unit <fosc> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# ROMs                             : 1  16x8-bit ROM                     : 1# Registers                        : 20  24-bit register                  : 1  1-bit register                   : 18  16-bit register                  : 1# Multiplexers                     : 1  4-bit 4-to-1 multiplexer         : 1# Adders/Subtractors               : 5  4-bit adder                      : 4  24-bit adder                     : 1# Comparators                      : 4  4-bit comparator greater         : 4=========================================================================Starting low level synthesis...Optimizing unit <fosc> ...=========================================================================Final ResultsOutput File Name                   : foscOutput Format                      : NGCOptimization Criterion             : SpeedTarget Technology                  : 9500Keep Hierarchy                     : YESMacro Preserve                     : YESMacro Generation                   : AutoXOR Preserve                       : YESMacro Statistics# Comparators                      : 4  4-bit comparator greater         : 4# Xors                             : 35  1-bit xor2                       : 35Design Statistics# Edif Instances                   : 390# I/Os                             : 14=========================================================================CPU : 3.85 / 4.01 s | Elapsed : 4.00 / 4.00 s --> EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.Done: completed successfully.

Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp fosc ngdbuild.rsp'


Creating TCL ProcessStarting: 'ngdbuild -f ngdbuild.rsp'Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -uc fosc.ucf -p XC9500 fosc.ngc fosc.ngd Reading NGO file "F:/    /Xilinx/fosc/fosc.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "Madd__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0000_Mxor_Result_1 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0000_Mxor_Result_2 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0000_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0000_Mxor_Result_3 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0001_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0001_Mxor_Result_1 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0001_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0001_Mxor_Result_2 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0001_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0001_Mxor_Result_3 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0002_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0002_Mxor_Result_1 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0002_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0002_Mxor_Result_2 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0002_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0002_Mxor_Result_3 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0003_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0003_Mxor_Result_1 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0003_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0003_Mxor_Result_2 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0003_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0003_Mxor_Result_3 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_1 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_10"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_10 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_11"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_11 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_12"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_12 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_13"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_13 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_14"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_14 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_15"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_15 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_16"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_16 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_17"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_17 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_18"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_18 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_19"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_19 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_2 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_20"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_20 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_21"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_21 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_22"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_22 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_23"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_23 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_3 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_4"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_4 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_5"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_5 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_6"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_6 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_7"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_7 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_8"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_8 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_count_1_Mxor_Result_9"...WARNING:LBEngine:353 - Module Madd__old_count_1_Mxor_Result_9 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Annotating constraints to design from file "fosc.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "fosc.ngd" ...Writing NGDBUILD log file "fosc.bld"...NGDBUILD done.Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -tcl -command _cpldfit.tcl'


Creating TCL ProcessStarting: 'cpldfit -f _cpldfit.rsp fosc.ngd'Release 4.1WP3.x - X9K/XPLA Optimizer/Partitioner E.33Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Considering device XC95108-PC84.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 70 equations into 6 function blocks.WARNING:Cpld - Unable to map all desired signals into function block, FB6,   because too many function block product terms are required. Buffering output   signal lddat<5> to allow all signals assigned to this function block to be   placed........................Design fosc has been optimized and fit into device XC95108-7-PC84.Tcl _cpldfit.tcl detected that program 'cpldfit -f _cpldfit.rsp fosc.ngd' completed successfully.Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command hprep6 -i fosc -r int -a -l fosc.log -n fosc '


Starting: 'hprep6 -i fosc -r int -a -l fosc.log -n fosc 'Release 4.1WP3.x - Programming File Generator E.33Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.EXEWRAP detected that program 'hprep6' completed successfully.Done: completed successfully.

Launching: 'impact -f __impact.rsp'