Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format                       : VERILOGInput File Name                    : buzz1.prj---- Target ParametersTarget Device                      : XC9500Output File Name                   : buzz1Output Format                      : NGCTarget Technology                  : 9500---- Source OptionsTop Module Name                    : buzz1Automatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Flip-Flop Type                 : DMux Extraction                     : YESResource Sharing                   : YESComplex Clock Enable Extraction    : YES---- Target OptionsAdd IO Buffers                     : YESEquivalent register Removal        : YESMacro Generator                    : AutoMACRO Preserve                     : YESXOR Preserve                       : YES---- General OptionsOptimization Criterion             : SpeedOptimization Effort                : 1Check Attribute Syntax             : YESKeep Hierarchy                     : YES---- Other Optionswysiwyg                            : NO========================================================================= Compiling source file : buzz1.prjCompiling included source file 'buzz1.v'Module <buzz1> compiled.Continuing compilation of source file 'buzz1.prj'Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'Continuing compilation of source file 'buzz1.prj'No errors in compilationAnalysis of file <buzz1.prj> succeeded.  Starting Verilog synthesis. Analyzing top module <buzz1>.Module <buzz1> is correct for synthesis.Synthesizing Unit <buzz1>.    Related source file is buzz1.v.    Found 20-bit comparator equal for signal <$n0017> created at line 13.    Found 20-bit adder for signal <$old_counter_1>.    Found 1-bit register for signal <buzzout_reg>.    Found 20-bit register for signal <counter>.    Summary:	inferred  21 D-type flip-flop(s).	inferred   1 Adder/Subtracter(s).	inferred   1 Comparator(s).Unit <buzz1> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 2  20-bit register                  : 1  1-bit register                   : 1# Adders/Subtractors               : 1  20-bit adder                     : 1# Comparators                      : 1  20-bit comparator equal          : 1=========================================================================Starting low level synthesis...Optimizing unit <buzz1> ...=========================================================================Final ResultsOutput File Name                   : buzz1Output Format                      : NGCOptimization Criterion             : SpeedTarget Technology                  : 9500Keep Hierarchy                     : YESMacro Preserve                     : YESMacro Generation                   : AutoXOR Preserve                       : YESMacro Statistics# Xors                             : 39  1-bit xor2                       : 39Design Statistics# Edif Instances                   : 390# I/Os                             : 18=========================================================================CPU : 4.07 / 4.23 s | Elapsed : 5.00 / 5.00 s -->