ISE Auto-Make Log File-----------------------

Starting: 'jhdparse @_buzz.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    buzz.v
Writing buzz.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

ISE Auto-Make Log File-----------------------

Starting: 'jhdparse @_buzz2.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    buzz2.v
Writing buzz2.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

ISE Auto-Make Log File-----------------------

Updating: Assign Pins (ChipViewer)

Starting: 'exewrap @__buzz2_2prj_exewrap.rsp'


Creating TCL ProcessDone: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn buzz2.xst -ofn buzz2.syr'


Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn buzz2.xst -ofn buzz2.syr 'Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format                       : VERILOGInput File Name                    : buzz2.prj---- Target ParametersTarget Device                      : XC9500Output File Name                   : buzz2Output Format                      : NGCTarget Technology                  : 9500---- Source OptionsTop Module Name                    : buzz2Automatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Flip-Flop Type                 : DMux Extraction                     : YESResource Sharing                   : YESComplex Clock Enable Extraction    : YES---- Target OptionsAdd IO Buffers                     : YESEquivalent register Removal        : YESMacro Generator                    : AutoMACRO Preserve                     : YESXOR Preserve                       : YES---- General OptionsOptimization Criterion             : SpeedOptimization Effort                : 1Check Attribute Syntax             : YESKeep Hierarchy                     : YES---- Other Optionswysiwyg                            : NO========================================================================= Compiling source file : buzz2.prjCompiling included source file 'buzz2.v'Module <buzz2> compiled.Continuing compilation of source file 'buzz2.prj'Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'Continuing compilation of source file 'buzz2.prj'No errors in compilationAnalysis of file <buzz2.prj> succeeded.  Starting Verilog synthesis. Analyzing top module <buzz2>.WARNING:Xst:905 - "buzz2.v", line 16: The signals <counter> are missing in the sensitivity list of always block.Module <buzz2> is correct for synthesis.Synthesizing Unit <buzz2>.    Related source file is buzz2.v.    Found 31-bit up counter for signal <counter>.    Summary:	inferred   1 Counter(s).Unit <buzz2> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Counters                         : 1  31-bit up counter                : 1=========================================================================Starting low level synthesis...Optimizing unit <buzz2> ...=========================================================================Final ResultsOutput File Name                   : buzz2Output Format                      : NGCOptimization Criterion             : SpeedTarget Technology                  : 9500Keep Hierarchy                     : YESMacro Preserve                     : YESMacro Generation                   : AutoXOR Preserve                       : YESMacro Statistics# Xors                             : 30  1-bit xor2                       : 30Design Statistics# Edif Instances                   : 156# I/Os                             : 18=========================================================================CPU : 2.20 / 2.36 s | Elapsed : 2.00 / 2.00 s --> EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.Done: completed successfully.

Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp buzz2 ngdbuild.rsp'


Creating TCL ProcessStarting: 'ngdbuild -f ngdbuild.rsp'Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -uc buzz2.ucf -p XC9500 buzz2.ngc buzz2.ngd Reading NGO file "F:/    /Xilinx/buzz/buzz2.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_1 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_10"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_10 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_11"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_11 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_12"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_12 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_13"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_13 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_14"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_14 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_15"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_15 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_16"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_16 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_17"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_17 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_18"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_18 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_19"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_19 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_2 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_20"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_20 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_21"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_21 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_22"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_22 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_23"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_23 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_24"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_24 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_25"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_25 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_26"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_26 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_27"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_27 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_28"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_28 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_29"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_29 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_3"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_3 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_30"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_30 : All styles   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_4"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_4 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_5"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_5 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_6"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_6 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_7"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_7 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_8"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_8 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "counter_Madd__n0000_Mxor_Result_9"...WARNING:LBEngine:353 - Module counter_Madd__n0000_Mxor_Result_9 : All styles for   SIMPLE_GATES are implemented identically  for the XC9500 family.Annotating constraints to design from file "buzz2.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "buzz2.ngd" ...Writing NGDBUILD log file "buzz2.bld"...NGDBUILD done.Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -tcl -command _chipview.tcl'


Creating TCL ProcessStarting: 'ChipView.bat -f buzz2.ngd -uc buzz2.ucf -dev XC95108-7-PC84'Tcl _chipview.tcl detected that program 'ChipView.bat -f buzz2.ngd -uc buzz2.ucf -dev XC95108-7-PC84' completed successfully.Starting: 'chkdate'Tcl _chipview.tcl detected that program 'chkdate' completed successfully.Existing implementation results (if any) will be retained.