/* SPI Control Registers                                  */
#define SPICTL  (0x1000)  /* SPI Control Register         */
#define SPIFLG  (0x1001)  /* SPI Flag register            */
#define SPIBAUD (0x1005)  /* SPI baud setup register      */

/* SPI DMA Registers                                      */
#define IISPI   (0x1080)  /* Internal DMA address         */
#define IMSPI   (0x1081)  /* Internal DMA access modifier */
#define CSPI    (0x1082)  /* Number of words to transfers */
#define CPSPI   (0x1083)  /* Points to next DMA parameters*/
#define SPIDMAC (0x1084)  /* SPI DMA control register     */

/*SPIFLG bits                                             */
#define DS0EN   (0x0001) /* enable SPI device select 0    */
#define SPIFLG0 (0x0100) /* manually set SPIFLG0 state    */
#define SPIFLG1 (0x0200) /* manually set SPIFLG1 state    */
#define SPIFLG2 (0x0400) /* manually set SPIFLG2 state    */
#define SPIFLG3 (0x0800) /* manually set SPIFLG3 state    */

/*SPIDMAC bits                                            */
#define SPIDEN  (0x0001) /* enable DMA on the SPI port    */
#define SPIRCV  (0x0002) /* set to have DMA receive       */
#define SPICHEN (0x0010) /* set to enable DMA chaining    */

/*SPICTL bits                                             */
#define TIMOD2  (0x0002) /* Use DMA for transfers         */
#define SENDZ   (0x0004) /* when TXSPI empty, MOSI sends 0*/
#define WL32    (0x0100) /* SPI Word Length = 32          */
#define SPIMS   (0x1000) /* SPI Master if 1, Slave if 0   */
#define SPIEN   (0x4000) /* SPI Port Enable               */
#define CLKPL   (0x0800) /* if 1, rising edge samples data*/
#define CPHASE  (0x0400) /* if 1, data's sampled on second*/
                         /*  (middle) edge of SPICLK cycle*/

/*========================================================*/
.section/dm seg_dmda;

/* Destinations for incoming data                         */
.var dest_bufC[8];
.var dest_bufB[8];
.var dest_bufA[8];


/* Transfer Control Blocks (TCB's)                        */
.var first_tcb[]=
        (0x7FFFF&second_tcb + 3), /* for CPSPI (next tcb) */
              LENGTH(dest_bufB), /* for CSPI (next count) */
                  1,           /* for IMSPI (next modify) */
                  dest_bufB;    /* for IISPI (next index) */

.var second_tcb[]= 0,         /* null CPSPI ends chain    */
              LENGTH(dest_bufC), /* count for final DMA   */
                   1,         /* IM for final DMA         */
                   dest_bufC; /* II for final DMA         */

/* NOTE: Chain Pointer registers must point to the LAST   */
/*        location in the TCB, "tcb + 3"  .    */

/*Main code section */
.global _main;
.section/pm seg_pmco;
_main:
/* clear SPI settings                                     */
r0=0;
dm(SPICTL)=r0;
dm(SPIFLG)=r0;
dm(SPIDMAC)=r0;

/* setup first DMA in chain */
ustat3=8;         dm( CSPI)=ustat3; /* count = 8 words    */
ustat3=1;         dm(IMSPI)=ustat3; /* step size = 1      */
ustat3=dest_bufA; dm(IISPI)=ustat3; /* point to dest_bufA */

/* set the SPI baud rate to CCLK/4*64 (781.25KHz @ 200MHz)*/
ustat3 = 0x64;
dm(SPIBAUD)=ustat3;

/* configure DSP's SPI slave-select signals               */
ustat3= DS0EN|  /*enable SPI slave device select zero     */
        SPIFLG3|SPIFLG2|SPIFLG1;/* Set SPIFLG0 low to     */
dm(SPIFLG) = ustat3;   /*select SPI slave on FLAG0 pin    */

/* configure SPI port to power-on settings                */
ustat3 = CPHASE| /* sample MISO on second edge of SPICLK  */
         CLKPL|   /* sampling edge of SPICLK is rising    */
         WL32|   /* 32-bit words */
         SPIMS|  /* Master mode (internal SPICLK)         */
         SPIEN|  /* Enable SPI port */
         SENDZ|  /* when TXSPI empty, MOSI sends zeros    */
         TIMOD2; /* Start SPICLK when DMA is enabled      */
dm(SPICTL)=ustat3;

/*configure SPI for chained recieve DMA operation         */
ustat3= SPIRCV|  /* DMA direction = receive               */
        SPICHEN| /* enable DMA chaining                   */
        SPIDEN;  /* enabling DMA initiates the transfer   */
dm(SPIDMAC)=ustat3;

/* 1st DMA starts when a valid address is written to CPSPI*/
ustat3=(0x7FFFF&(first_tcb+3));
dm(CPSPI)=ustat3; /* point to tcb_A   */

_main.end: jump(pc,0);
/*========================================================*/