This experiment uses the Blackfi n BF533/BF537 EZ-KIT to run a simple FIR fi lter on stereo
channels at a sampling frequency of 48 kHz. The
CYCLE register is embedded in the main
program (
process_data.c) to benchmark the time needed to process two FIR fi lters. A
background telemetry channel (BTC) is set up to display the cycle count.
This Document provides the High Level Design specification for the Bootloader development and library porting for ADSP-BF533 based EZ-KIT Lite Board and STAMP Board. This document is meant to be the one of the inputs for the System Test Plan and the overall implementation of the same. This document also details the approach and assumptions made for the design
