/* Register definitions */
#define SRU_CLK3    0x2434
#define SRU_PIN0    0x2460
#define SRU_PBEN0   0x2478
#define PCG_CTLB0   0x24C2
#define PCG_CTLB1   0x24C3
#define PCG_PW      0x24C4

/* SRU definitions */
#define PCG_CLKB_P      0x39
#define PCG_FSB_P       0x3B
#define PBEN_HIGH_Of    0x01

//Bit Positions
#define DAI_PB02        6
#define PCG_PWB         16

/* Bit definitions */
#define ENFSB       0x40000000
#define ENCLKB      0x80000000

/* Main code section */
.global _main;
.section/pm seg_pmco;
_main:
/* Route PCG Channel B clock to DAI Pin 1 via SRU */
/* Route PCG Channel B frame sync to DAI Pin 2 via SRU */
r0=PCG_CLKB_P|(PCG_FSB_P<<DAI_PB02);
dm(SRU_PIN0)=r0;

/* Enable DAI Pins 1 & 2 as outputs */
r0=PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PB02);
dm(SRU_PBEN0)=r0;

r0=(100<<PCG_PWB); /* PCG Channel B FS Pulse width = 100 */
dm(PCG_PW)=r0;

r2=1000; /* Define 20-bit Phase Shift */
r0=(ENFSB|ENCLKB| /*Enable PCG Channel B Clock and FS*/
        1000000); /* FS Divisor = 1000000 */
r1=lshift r2 by -10;
/* Deposit the upper 10-bits of the Phase Shift in the */
/* correct position in PCG_CTLB0 (Bits 20-29) */
r1=fdep r1 by 20:10;
r0=r0 or r1; /* Phase Shift 10-19 = 0 */
dm(PCG_CTLB0)=r0;


r0=(100000);  /* Clk Divisor = 100000 */
            /* Use CLKIN as clock source */
/* Deposit the lower 10-bits of the Phase Shift in the */
/* correct position in PCG_CTLB1 (Bits 20-29) */
r1=fdep r2 by 20:10;
r0=r0 or r1; /* Phase Shift 10-19 = 0x3E8 */
dm(PCG_CTLB1)=r0;
//----------------------------------------
_main.end: jump(pc,0);