/* SPI Control Registers                                  */
#define SPICTL  (0x1000)  /* SPI Control Register         */
#define SPIFLG  (0x1001)  /* SPI Flag register            */
#define SPIBAUD (0x1005)  /* SPI baud setup register      */

/* SPI DMA Registers                                      */
#define IISPI   (0x1080)  /* Internal DMA address         */
#define IMSPI   (0x1081)  /* Internal DMA access modifier */
#define CSPI    (0x1082)  /* Number of words to transfers */
#define CPSPI   (0x1083)  /* Points to next DMA parameters*/
#define SPIDMAC (0x1084)  /* SPI DMA control register     */

/*SPIFLG bits                                             */
#define DS0EN   (0x0001) /* enable SPI device select 0    */
#define SPIFLG0 (0x0100) /* manually set SPIFLG0 state    */
#define SPIFLG1 (0x0200) /* manually set SPIFLG1 state    */
#define SPIFLG2 (0x0400) /* manually set SPIFLG2 state    */
#define SPIFLG3 (0x0800) /* manually set SPIFLG3 state    */

/*SPIDMAC bits                                            */
#define SPIDEN  (0x0001) /* enable DMA on the SPI port    */
#define SPIRCV  (0x0002) /* set to have DMA receive       */
#define SPICHEN (0x0010) /* set to enable DMA chaining    */

/*SPICTL bits                                             */
#define TIMOD2  (0x0002) /* Use DMA for transfers         */
#define SENDZ   (0x0004) /* when TXSPI empty, MOSI sends 0*/
#define WL32    (0x0100) /* SPI Word Length = 32          */
#define SPIMS   (0x1000) /* SPI Master if 1, Slave if 0   */
#define SPIEN   (0x4000) /* SPI Port Enable               */
#define CLKPL   (0x0800) /* if 1, rising edge samples data*/
#define CPHASE  (0x0400) /* if 1, data's sampled on second*/
                         /*  (middle) edge of SPICLK cycle*/

/*========================================================*/

/* Destinations for incoming data                         */
int dest_bufC[8];
int dest_bufB[8];
int dest_bufA[8];


/* Transfer Control Blocks (TCB's)                        */
int second_tcb[]= {0,         /* null CPSPI ends chain    */
                   sizeof(dest_bufC), /* count for final DMA   */
                   1,         /* IM for final DMA         */
                   (int) dest_bufC}; /* II for final DMA         */


int first_tcb[]= {0, /* for CPSPI (next tcb) */
                  sizeof(dest_bufB), /* for CSPI (next count) */
                  1,           /* for IMSPI (next modify) */
                  (int) dest_bufB};    /* for IISPI (next index) */

/* NOTE: Chain Pointer registers must point to the LAST   */
/*        location in the TCB, "tcb + 3"  .    */

/*Main code section */
main(){

     first_tcb[0]= (0x7FFFF&((int)second_tcb + 3)); /* for CPSPI (next tcb) */     
/* clear SPI settings                                     */
     *(volatile int *)SPICTL = 0;
     *(volatile int *)SPIFLG = 0;
     *(volatile int *)SPIDMAC = 0;

/* setup first DMA in chain */
     *(volatile int *)CSPI = sizeof(dest_bufA); /* count = 8 words    */
     *(volatile int *)IMSPI = 1;      /* step size = 1      */
     *(volatile int *)IISPI = (int) dest_bufA; /* point to dest_bufA */

/* set the SPI baud rate to CCLK/4*64 (781.25KHz @ 200MHz)*/
     *(volatile int *)SPIBAUD = 0x64;

/* configure DSP's SPI slave-select signals               */
     *(volatile int *)SPIFLG = DS0EN|  /*enable SPI slave device select zero     */
        SPIFLG3|SPIFLG2|SPIFLG1;/* Set SPIFLG0 low to     */
         /*select SPI slave on FLAG0 pin    */

/* configure SPI port to power-on settings                */
     *(volatile int *)SPICTL = CPHASE| /* sample MISO on second edge of SPICLK  */
         CLKPL|   /* sampling edge of SPICLK is rising    */
         WL32|   /* 32-bit words */
         SPIMS|  /* Master mode (internal SPICLK)         */
         SPIEN|  /* Enable SPI port */
         SENDZ|  /* when TXSPI empty, MOSI sends zeros    */
         TIMOD2; /* Start SPICLK when DMA is enabled      */

/*configure SPI for chained recieve DMA operation         */
     *(volatile int *)SPIDMAC = SPIRCV|  /* DMA direction = receive               */
        SPICHEN| /* enable DMA chaining                   */
        SPIDEN;  /* enabling DMA initiates the transfer   */

/* 1st DMA starts when a valid address is written to CPSPI*/
     *(volatile int *)CPSPI = (0x7FFFF&((int) first_tcb+3));
/* point to tcb_A   */
/*========================================================*/
}