?? test.v
字號(hào):
module test;reg i1, i2;wire out; AND2 m1(o1,i1,i2); and (out, i1,i2); initial begin $monitor($time,,,"in=%b out=%b ",{i1,i2},o1); {i1,i2} = 4'b0; repeat(10) #10 {i1,i2} = {i1,i2} + 1; #0 if (o1 !== out) $display ("Error: i1=%b i2=%b Expected out=%b Actual out=%b",i1,i2,out,o1); endendmodulemodule AND2(o1,i1,i2);input i1, i2;output o1;reg o1; initial $and(o1,i1,i2);endmodule?? 快捷鍵說(shuō)明
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