Classic Timing Analyzer report for dianzirili
Fri Oct 26 00:14:54 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. Clock Setup: 'mode'
  7. Clock Setup: 'turn'
  8. Clock Hold: 'clk'
  9. Clock Hold: 'mode'
 10. Clock Hold: 'turn'
 11. tsu
 12. tco
 13. tpd
 14. th
 15. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                  ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------+--------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                                    ; From    ; To           ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------+--------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 3.251 ns                                       ; change  ; loop5[1]     ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 19.973 ns                                      ; min1[0] ; alert        ; clk        ; --       ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 7.550 ns                                       ; clk_1k  ; alert        ; --         ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 8.454 ns                                       ; turn    ; sec1[0]      ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A                                      ; None          ; 88.48 MHz ( period = 11.302 ns )               ; sec1[5] ; minclk       ; clk        ; clk      ; 0            ;
; Clock Setup: 'turn'          ; N/A                                      ; None          ; 109.71 MHz ( period = 9.115 ns )               ; min1[2] ; hclk         ; turn       ; turn     ; 0            ;
; Clock Setup: 'mode'          ; N/A                                      ; None          ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; m[1]    ; m[0]         ; mode       ; mode     ; 0            ;
; Clock Hold: 'clk'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; mon1[2] ; mon1[3]      ; clk        ; clk      ; 207          ;
; Clock Hold: 'mode'           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; m[2]    ; min[0]$latch ; mode       ; mode     ; 81           ;
; Clock Hold: 'turn'           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; mon1[2] ; mon1[3]      ; turn       ; turn     ; 33           ;
; Total number of failed paths ;                                          ;               ;                                                ;         ;              ;            ;          ; 321          ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+---------+--------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;