?? edge.vhd
字號:
library IEEE;
use IEEE.std_logic_1164.all;
entity EDGE is
port (
ADDATA: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
VOLTAGE_TRI : IN std_logic_vector (7 downto 0);
TRIGGER : OUT STD_LOGIC
);
end entity;
architecture ART of EDGE is
begin
process( VOLTAGE_TRI,ADDATA )
begin
IF ( VOLTAGE_TRI < ADDATA) then
TRIGGER<='1';
ELSE
TRIGGER<='0';
END IF;
END PROCESS;
end architecture;
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