`timescale 1ns/10psmodule testbench;reg [15:0] a;reg [15:0] b;reg      cin;wire [15:0] s;wire    cout;    add16_advu0( .vA(a), .vB(b), .vS(s), .cin(cin), .cout(cout));    initial begin    a=32'h1234;    b=32'h2345;    cin=0;    #10    a=32'h3333;    b=32'h4444;    cin=0;    #10    a=32'h1987;    b=32'h2377;    cin=1;    #10    $stop;    end    endmodule