library IEEE;
use IEEE.std_logic_1164.all;

entity char_87seg is           --能同時在8個7段譯碼器上顯示不同的符號
	port
		(    
		      CIN : in  std_logic_vector(2 downto 0);
		 DISPLAY0 : out std_logic_vector(0 to 6);
		 DISPLAY1 : out std_logic_vector(0 to 6);  
		 DISPLAY2 : out std_logic_vector(0 to 6);
		 DISPLAY3 : out std_logic_vector(0 to 6);
		 DISPLAY4 : out std_logic_vector(0 to 6);
		 DISPLAY5 : out std_logic_vector(0 to 6);
		 DISPLAY6 : out std_logic_vector(0 to 6);
		 DISPLAY7 : out std_logic_vector(0 to 6)
		);
end char_87seg;


architecture bhav of char_87seg is
	component cnt8
		port
		( 
		 add8 : in  std_logic_vector(2 downto 0);
	     cout : out std_logic_vector(2 downto 0)
		);
	end component;
	
	component char_7seg
		port(
			    Cin : in  std_logic_vector(2 downto 0);
			Display : out std_logic_vector(0 to 6)
		);
	end component;
	
	signal OUT0 : std_logic_vector(2 downto 0);
	signal OUT1 : std_logic_vector(2 downto 0);
	signal OUT2 : std_logic_vector(2 downto 0);
	signal OUT3 : std_logic_vector(2 downto 0);
	signal OUT4 : std_logic_vector(2 downto 0);
	signal OUT5 : std_logic_vector(2 downto 0);
	signal OUT6 : std_logic_vector(2 downto 0);
	signal OUT7 : std_logic_vector(2 downto 0);
	
	begin
		ADD0 : cnt8      port map(add8=>CIN , cout=>OUT0);
		SEG1 : char_7seg port map(Cin=>OUT0 , Display=>DISPLAY0);
		
		ADD1 : cnt8      port map(add8=>OUT0 , cout=>OUT1);
		SEG2 : char_7seg port map(Cin=>OUT1 , Display=>DISPLAY1);
		
		ADD2 : cnt8      port map(add8=>OUT1 , cout=>OUT2);
		SEG3 : char_7seg port map(Cin=>OUT2 , Display=>DISPLAY2);
		
		ADD3 : cnt8      port map(add8=>OUT2 , cout=>OUT3);
		SEG4 : char_7seg port map(Cin=>OUT3 , Display=>DISPLAY3);
		
		ADD4 : cnt8      port map(add8=>OUT3 , cout=>OUT4);
		SEG5 : char_7seg port map(Cin=>OUT4 , Display=>DISPLAY4);
		
		ADD5 : cnt8      port map(add8=>OUT4 , cout=>OUT5);
		SEG6 : char_7seg port map(Cin=>OUT5 , Display=>DISPLAY5);
		
		ADD6 : cnt8      port map(add8=>OUT5 , cout=>OUT6);
		SEG7 : char_7seg port map(Cin=>OUT6 , Display=>DISPLAY6);
		
		ADD7 : cnt8      port map(add8=>OUT6 , cout=>OUT7);
		SEG8 : char_7seg port map(Cin=>OUT7 , Display=>DISPLAY7);
end architecture;