library IEEE;
use IEEE.std_logic_1164.all;

entity HELO is           --在7段譯碼器上能顯示H,E,L,O
	port(
			    Cin : in  std_logic_vector(2 downto 0);
			Display : out std_logic_vector(6 downto 0)
		);
end entity;

architecture bhav of HELO is

--	signal D : std_logic_vector(0 to 6);
begin	 
	process(Cin)
		begin
			case Cin is
				when "000"  => Display <="0001001";    --H  
				when "001"  => Display <="0000110";    --E
				when "010"  => Display <="1000111";    --L
				when "011"  => Display <="1000000";    --O
				when "100"  => Display <="1111111";    --無
				when "101"  => Display <="1111111";    --無
				when "110"  => Display <="1111111";    --無
				when "111"  => Display <="1111111";    --無
				when others => NULL;
			end case;
	end process;
end architecture;