/**********************************************************************************  Xilinx, Inc. 2002                 www.xilinx.com****  XAPP 266 - Synthesizable FCRAM Controller*************************************************************************************  File name :       controller.v****  Description :     Main FCRAM controller block. This includes the following**                    features:**                    - The main controller state machine that controlls the **                    initialization process upon power up, as well as the **                    read, write, and refresh commands. **                    - Accepts and decodes the user commands.**                    - Generates all FCRAM commands via the three**                    FCRAM control pins (PDB, CSB, FN).**                    - Generates control signals for other modules, including**                    the control signals for the dqs_en block.****  Date - revision : 01/15/2002 - v 1.0****  Author :          CLF****  Contact : e-mail  hotline@xilinx.com**            phone   + 1 800 255 7778 ****  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are **              provided to you "as is". Xilinx and its licensors make and you **              receive no warranties or conditions, express, implied, **              statutory or otherwise, and Xilinx specifically disclaims any **              implied warranties of merchantability, non-infringement, or **              fitness for a particular purpose. Xilinx does not warrant that **              the functions contained in these designs will meet your **              requirements, or that the operation of these designs will be **              uninterrupted or error free, or that defects in the Designs **              will be corrected. Furthermore, Xilinx does not warrant or **              make any representations regarding use or the results of the **              use of the designs in terms of correctness, accuracy, **              reliability, or otherwise. ****              LIMITATION OF LIABILITY. In no event will Xilinx or its **              licensors be liable for any loss of data, lost profits, cost **              or procurement of substitute goods or services, or for any **              special, incidental, consequential, or indirect damages **              arising from the use or operation of the designs or **              accompanying documentation, however caused and on any theory **              of liability. This limitation will apply even if Xilinx **              has been advised of the possibility of such damage. This **              limitation shall apply not-withstanding the failure of the **              essential purpose of any limited remedies herein. ****  Copyright