LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY MyCounter IS 
	generic
	(
		N		: integer;
		Length0 : std_logic_vector;
		Length1 : std_logic_vector;
		Length2 : std_logic_vector;
		Length3 : std_logic_vector
	);
	port
	(
		fs_clk 	:  IN  STD_LOGIC;
		RstD 	:  IN  STD_LOGIC;
		clk 	:  out  STD_LOGIC;
		q_ck 	:  OUT  std_logic_vector(N-1 downto 0)
	);
END MyCounter;

ARCHITECTURE a OF MyCounter IS
	signal q	: std_logic_vector(N-1 downto 0);
	signal clkD	: std_logic;		--	clkD delay
BEGIN 

	clk <= clkD;
	q_ck <= q;
	process(fs_clk, q, clkD)
	begin
		if rising_edge(fs_clk) then
			if RstD = '1' then
				q <= Length0;
				clkD <= '0';
			elsif q = Length3 then			--	1440
				q <= Length1;
			else
				q <= q + '1';
				case q is 
					when Length1 => clkD <= '1';
					when Length2 => clkD <= '0';
					when others  => clkD <= clkD;
				end case;
			end if;
		end if;		
	end process;

END a;