?? qiangda.vhd
字號:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY qiangda IS
PORT( CLK,START,CLR_1,CLR_2 : IN BIT;
ADD10,ADD20,ADD30 : IN BIT;
SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
LED : OUT INTEGER RANGE 1 TO 2;
mark_1 : OUT INTEGER RANGE 0 TO 255;
mark_2 : OUT INTEGER RANGE 0 TO 255);
END qiangda;
ARCHITECTURE rtl OF qiangda IS
BEGIN
PROCESS (START,CLK,ADD10,ADD20,ADD30,CLR_1,CLR_2)
VARIABLE cnt_1 : INTEGER:=0;
VARIABLE cnt_2 : INTEGER:=0;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (START='1') THEN
CASE SEL IS
WHEN "01"=>
IF (CLR_1='1') THEN cnt_1 :=0;
ELSIF (ADD10 = '1') THEN cnt_1 := cnt_1 + 10;
ELSIF (ADD20 = '1') THEN cnt_1 := cnt_1 + 20;
ELSIF (ADD30 = '1') THEN cnt_1 := cnt_1 + 30;
END IF;
mark_1 <= cnt_1;
WHEN "10"=>
IF (CLR_2='1') THEN cnt_2 :=0;
ELSIF (ADD10 = '1') THEN cnt_2 := cnt_2 + 10;
ELSIF (ADD20 = '1') THEN cnt_2 := cnt_2 + 20;
ELSIF (ADD30 = '1') THEN cnt_2 := cnt_2 + 30;
END IF;
mark_2 <= cnt_2;
WHEN OTHERS=>
mark_1 <= cnt_1;
mark_2 <= cnt_2;
END CASE;
END IF;
END IF;
END PROCESS;
PROCESS (SEL,START)
BEGIN
IF (START='1') THEN
IF (SEL="01" THEN LED<=1;
ELSIF (SEL="10" THEN LED<=2;
END IF;
ELSE
LED<=0;
END IF;
END PROCESS;
END rtl;
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